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參數(shù)資料
| 型號： | MB40C328 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 8-bit 100 MSPS A/D Converter |
| 中文描述： | 8位100 MSPS的A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 163K |
| 代理商： | MB40C328 |
12
MB40C328
I
TIMING CHART 4
Two-phase CLK input mode (CLKA, CLKB)
CLK = “L” (DV
SS
) or “H” (DV
DD
)
CLKA = CLKB = 50 MHz (max)
CKSEL = “L” (AV
SS
)
DSEL = “L” (DV
SS
)
RESET = “H” (DV
DD
) or “L” (DV
SS
)
CE = “L” (AV
SS
)
OE = “L” (DV
SS
)
V
INA
input
—
Sampling (A ch) at CLKA falling
Sampling (B ch) at CLKB falling
D
A0
to D
A7
—
Output (after 2.5 CLK + t
pdD
from Sampling) at CLKA rising
D
B0
to D
B7
—
Output (after 2.5 CLK + t
pdD
from Sampling) at CLKB rising
t
pdD
(max)
t
pdD
(typ)
t
pdD
(min)
t
pdD
(max)
t
pdD
(typ)
t
pdD
(min)
V
IHD
V
ILD
V
IHD
V
ILD
V
OHD
V
OLD
D
A0
to
D
A7
V
OHD
V
OLD
D
B0
to
D
B7
V
OHD
V
OLD
CLKOA
V
OHD
V
OLD
CLKOB
t
WD
t
WD
+
t
WD
+
t
AD
N(Ach)
N
+
1(Bch)
N
6
N
5
N
3
N
1
t
pdDO
(max)
t
pdDO
(typ)
N
+
1
N
4
N
2
N
+
2(Ach) N
+
3(Bch) N
+
4(Ach) N
+
5(Bch) N
+
6(Ach) N
+
7(Bch)
t
AD
t
WD
t
r
t
f
0.5 V
t
r
t
f
0.5 V
1.5 V
1.5 V
N
DV
DD
0.4 V
0.4 V
0.4 V
DV
DD
0.4 V
0.4 V
t
pdDO
(max.)
0.4 V
DV
DD
0.4 V
t
pdDO
(min)
t
pdDO
(typ)
t
pdDO
(min.)
DV
DD
0.4 V
DV
DD
0.5 V
DV
DD
0.5 V
D
A0
to
D
A7
CLKA
input
CLKB
input
V
INA
input
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MB40C328PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit 100 MSPS A/D Converter |
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| MB40C338PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:3 ch 8-bit 162 MSPS A/D Converter |
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