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參數(shù)資料
| 型號： | MB40C338PFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | ADC |
| 英文描述： | 3 ch 8-bit 162 MSPS A/D Converter |
| 中文描述： | 3-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP120 |
| 封裝： | 16 X 16 MM, 0.50 MM PITCH, PLASTIC, LQFP-120 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 247K |
| 代理商： | MB40C338PFV |
MB40C338
4
(Continued)
Parameter
Note: The values in parentheses are standard.
Symbol
Description
99
EXPCLKB
Differential clock (negative-phase) input pin for A/D converter
Fix to “H” level when unused.
PECL level
100
EXPCLK
Differential clock (positive-phase) input pin for A/D converter
Fix to “L” level when unused.
8
PCLP
Clamp pulse input pin
4
CE
Power down at CE input “H” (internal pull-up resistor)
Internal current setting pin (Add 12 k
for AV
SS
)
Delay sync signal output pin
113
R
REF
103
DSYNC
102
DSYNCB
Inverted delay sync signal output pin
95
CLK
Clock output pin (See “
I
TIMING DIAGRAM”.)
94
CLKB
97
ADCLKA
96
ADCLKB
83 to 90
61 to 68
39 to 46
RD
A7
to RD
A0
GD
A7
to GD
A0
BD
A7
to BD
A0
Digital output pin (Port A)
RD
A7
, GD
A7
, BD
A7
: MSB
RD
A0
, GD
A0
, BD
A0
: LSB
71 to 78
51 to 58
29 to 36
RD
B7
to RD
B0
GD
B7
to GD
B0
BD
B7
to BD
B0
Digital output pin (Port B)
RD
B7
, GD
B7
, BD
B7
: MSB
RD
B0
, GD
B0
, BD
B0
: LSB
101
COUT
PLL counter output pin
115
LPF
External capacitor/resistor connection pin
117
HHOLD
Phase detector operation is hold by input “H” level
118
HSYNC
Horizontal sync signal input pin
7
V
REF
Internal voltage output pin (Add 3.3μF for AV
SS
)
104
OF
Overflow output pin (“H” level output at overflow)
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| MB40C338V | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:3 ch 8-bit 162 MSPS A/D Converter |
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| MB40C348 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:3 ch 8-bit 100 MSPS A/D Converter |
| MB40C348PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:3 ch 8-bit 100 MSPS A/D Converter |
| MB40C348V | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:3ch 8-bit 100 MSPS A/D Converter |
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