參數(shù)資料
型號(hào)： MB81116422A-125
廠商： Fujitsu Limited
英文描述： CMOS 2×2M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 2×2M ×4 位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 2 × 200萬× 4位超頁模式動(dòng)態(tài)RAM（2 × 200萬的CMOS × 4位超級(jí)頁面存取模式動(dòng)態(tài)內(nèi)存）
文件頁數(shù)： 20/43頁
文件大小： 275K
代理商： MB81116422A-125
20
MB81116422A-125/-100/-84/-67
BURST MODE OPERATION AND BURST TYPE (Continued)
When the full burst operation is executed at single write mode, Auto-precharge command is valid only at write
operation.
The burst type can be selected either sequential or interleave mode. But only the sequential mode is usable to
the full column burst. The sequential mode is an incremental decoding scheme within a boundary address to
be determined by burst length, it assigns +1 to the previous (or initial) address until reaching the end of boundary
address and then wraps round to least significant address (= 0).
FULL COLUMN BURST AND BURST STOP COMMAND (BST)
The full column burst is an option of burst length and available only at sequential mode of burst type. This full
column burst mode is repeatedly access to the same column. If burst mode reaches end of column address,
then it wraps round to first column address (= 0) and continues to count until interrupted by the news read
(READ)/write (WRIT/BWRIT), precharge (PRE), or burst stop (BST) command. The selection of auto-precharge
option is illegal during the full column burst operation except write command at BURST READ & SINGLE WRITE
mode.
The BST command is applicable to terminated the full column burst operation and illegal during the burst
operation with length of 1, 2, 4, and 8. If the BST command is asserted during the full column burst mode, its
operation is terminated immediately and the internal state moves to Bank Active.
When read mode is interrupted by BST command, the output will be in High-Z.
For the detail rule, please refer to Timing Diagram-8.
When write mode is interrupted by BST command, the data to be applied at the same time with BST command
will be ignored.
BURST READ & SINGLE WRITE
The burst read and single write mode provides single word write operation regardless of its burst length. In this
mode, burst read operation does not be affected by this mode.
Burst
Length
Stating Column
Address
A
2
A
1
A
0
Sequential Mode
Interleave
2
X X 0
0 – 1
0 – 1
X X 1
1 – 0
1 – 0
4
X 0 0
0 – 1 – 2 – 3
0 – 1 – 2 – 3
X 0 1
1 – 2 – 3 – 0
1 – 0 – 3 – 2
X 1 0
2 – 3 – 0 – 1
2 – 3 – 0 – 1
X 1 1
3 – 0 – 1 – 2
3 – 2 – 1 – 0
8
0 0 0
0 – 1 – 2 – 3 – 4 – 5 – 6 – 7
0 – 1 – 2 – 3 – 4 – 5 – 6 – 7
0 0 1
1 – 2 – 3 – 4 – 5 – 6 – 7 – 0
1 – 0 – 3 – 2 – 5 – 4 – 7 – 6
0 1 0
2 – 3 – 4 – 5 – 6 – 7 – 0 – 1
2 – 3 – 0 – 1 – 6 – 7 – 4 – 5
0 1 1
3 – 4 – 5 – 6 – 7 – 0 – 1 – 2
3 – 2 – 1 – 0 – 7 – 6 – 5 – 4
1 0 0
4 – 5 – 6 – 7 – 0 – 1 – 2 – 3
4 – 5 – 6 – 7 – 0 – 1 – 2 – 3
1 0 1
5 – 6 – 7 – 0 – 1 – 2 – 3 – 4
5 – 4 – 7 – 6 – 1 – 0 – 3 – 2
1 1 0
6 – 7 – 0 – 1 – 2 – 3 – 4 – 5
6 – 7 – 4 – 5 – 2 – 3 – 0 – 1
1 1 1
7 – 0 – 1 – 2 – 3 – 4 – 5 – 6
7 – 6 – 5 – 4 – 3 – 2 – 1 – 0
相關(guān)PDF資料
PDF描述
MB81116422A-67 CMOS 2×2M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 2×2M ×4 位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
MB81116422A-84 CMOS 2×2M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 2×2M ×4 位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
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MB81116822A-125 CMOS 2×1M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2×1M ×8位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
MB81116822A-67 CMOS 2×1M ×8 BIT Hyper Page Mode Dynamic RAM(CMOS 2×1M ×8位超級(jí)頁面存取模式動(dòng)態(tài)RAM)
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