參數(shù)資料
型號(hào)： MB8117405A-60
廠商： Fujitsu Limited
英文描述： CMOS 4M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
中文描述： 的CMOS 4米× 4位超頁(yè)模式動(dòng)態(tài)RAM的CMOS（4米× 4位超級(jí)頁(yè)面存取模式動(dòng)態(tài)內(nèi)存）
文件頁(yè)數(shù)： 1/28頁(yè)
文件大?。?/td> 348K
代理商： MB8117405A-60
1
DS05-10196-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
CMOS 4M
HYPER PAGE MODE DYNAMIC RAM
×
4 BIT
MB8117405A-60/-70
CMOS 4,194,304
×
4 BIT Hyper Page Mode Dynamic RAM
I
DESCRIPTION
The Fujitsu MB8117405A is a fully decoded CMOS Dynamic RAM (DRAM) that contains 16,777,216 memory
cells accessible in 4-bit increments. The MB8117405A features a “hyper page” mode of operation whereby high-
speed random access of up to 1,024-bits of data within the same row can be selected. The MB8117405A DRAM
is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory
applications where very low power dissipation and high bandwidth are basic requirements of the design. Since
the standby current of the MB8117405A is very small, the device can be used as a non-volatile memory in
equipment that uses batteries for primary and/or auxiliary power.
The MB8117405A is fabricated using silicon gate CMOS and Fujitsu’s advanced four-layer polysilicon and two-
layer aluminum process. This process, coupled with advanced stacked capacitor memory cells, reduces the
possibility of soft errors and extends the time interval between memory refreshes. Clock timing requirements
for the MB8117405A are not critical and all inputs are TTL compatible.
I
PRODUCT LINE & FEATURES
Parameter
MB8117405A-60
MB8117405A-70
RAS Access Time
60 ns max.
70 ns max.
Randam Cycle Time
104 ns min.
124 ns min.
Address Access Time
30 ns max.
35 ns max.
CAS Access Time
15 ns max.
17 ns max.
Hyper Page Mode Cycle Time
25 ns min.
30 ns min.
Low Power
Dissipation
Operating current
577.5 mW max.
495 mW max.
Standby current
11 mW max. (TTL level)/5.5 mW max. (CMOS level)
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields. However, it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.
4,194,304 words
×
4 bit organization
Silicon gate, CMOS, Advanced Capacitor Cell
All input and output are TTL compatible
2048 refresh cycles every 32.8ms
Early Write or OE controlled write capability
RAS only, CAS-before-RAS, or Hidden Refresh
Hyper Page Mode, Read-Modify-Write capability
On chip substrate bias generator for high
performance
相關(guān)PDF資料
PDF描述
MB8117405A-70 CMOS 4M ×4 BIT Hyper Page Mode Dynamic RAM(CMOS 4M ×4 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM)
MB8117405B-50 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁(yè)面存取模式RAM)
MB8117405B-60 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁(yè)面存取模式RAM)
MB8117800A-70 CMOS 2 M ×8BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
MB8117800A-60 CMOS 2 M ×8BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁(yè)面存取模式動(dòng)態(tài)RAM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MB8117800A-60 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM
MB8117800A-70 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM
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