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參數(shù)資料
| 型號(hào)： | MB8117405B-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 4 M ×4 BITS Fast Page Mode Dynamic RAM(CMOS 4 M ×4 位快速頁面存取模式RAM) |
| 中文描述： | 4米× 4位快速頁面模式動(dòng)態(tài)RAM（的CMOS 4米× 4位快速頁面存取模式的RAM） |
| 文件頁數(shù)： | 6/31頁 |
| 文件大?。?/td> | 588K |
| 代理商： | MB8117405B-60 |
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6
MB8117405B-50/-60
DATA OUTPUTS
The three-state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical
to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes
Low. When a read or read-modify-write cycle is executed, valid outputs and High-Z state are obtained under the
following conditions:
t
RAC
:
from the falling edge of RAS when t
RCD
(max) is satisfied.
t
CAC
:
from the falling edge of CAS when t
RCD
is greater than t
t
AA
:
from column address input when t
RAD
is greater than t
t
OEA
:
from the falling edge of OE when OE is brought Low after t
RAC
, t
CAC
, or t
AA
.
t
OEZ
:
from OE inactive.
t
OFF
:
from CAS inactive while RAS inactive.
t
OFR
:
from RAS inactive while CAS inactive.
t
WEZ
:
from WE active while CAS inactive.
The data remains valid before either OE is inactive, or both RAS and CAS are inactive, or CAS is reactived.
When an early write is execute, the output buffers remain in a high-impedance state during the entire cycle.
RCD
(max).
(max), and t
RCD
(max) is satisfied.
RAD
HYPER PAGE MODE OF OPERATION
The hyper page mode of operation provides faster memory access and lower power dissipation. The hyper page
mode is implemented by keeping the same row address and strobing in successive column addresses. To satisfy
these conditions, RAS is held Low for all contiguous memory cycles in which row addresses are common. For
each page of memory (with column address locations), any of 1,024-bits can be accessed and, when multiple
MB8117405Bs are used, CAS is decoded to select the desired memory page. Hyper page mode operations
need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are
permitted. Hyper page mode features that output remains valid when CAS is inactive until CAS is reactivated.
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| MB8117800A-70 | CMOS 2 M ×8BIT Fast Page Mode DRAM(CMOS 2 M ×8 位快速頁面存取模式動(dòng)態(tài)RAM) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB8117800A-60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM |
| MB8117800A-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 M X 8 BIT FAST PAGE MODE DYNAMIC RAM |
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| MB812.833 | 功能描述:ACCY MOUNT BMM 3/4 58A RoHS:是 類別:RF/IF 和 RFID >> RF配件 系列:* 標(biāo)準(zhǔn)包裝:1 系列:* |
| MB-8120 | 制造商:Maxxtro 功能描述: |
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