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參數(shù)資料
| 型號： | MB81F643242C-10 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 4 X 512 K X 32 BIT SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 4 × 512 kX的32位同步動態(tài)隨機存儲器 |
| 文件頁數(shù)： | 24/56頁 |
| 文件大?。?/td> | 1001K |
| 代理商： | MB81F643242C-10 |
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24
MB81F643242C-60/-70/-10
Advanced Info (AE0.1E)
I
MULTI BANK OPERATION COMMAND TABLE
MINIMUM CLOCK LATENCY OR DELAY TIME FOR MULTI BANK OPERATION
Second
command
(other
bank)
M
Notes:
*1.
If t
RP
(min.)<CL
×
t
CK
, minimum latency is a sum of (BL+CL)
×
t
CK
.
Assume bank of the object is in Idle sate.
Assume output is in High-Z sate.
t
RRD
(min.) of other bank (second command will be asserted) is satisfied.
Assume other bank is in active, read or write state.
Assume t
RAS
(min.) is satisfied.
Assume other banks are not in READA/WRITA state.
Assume after the last data have been appeared on DQ.
If t
RP
(min.)<(CL-1)
×
t
CK
, minimum latency is a sum of (BL+CL-1)
×
t
CK
.
Assume no I/O conflict.
*2.
*3.
*4.
*5.
*6.
*7.
*8.
*9.
*10.
Illegal Command
*5
*5,*6
*5
*5,*6
First
command
MRS
t
RSC
t
RSC
t
RSC
t
RSC
t
RSC
t
RSC
t
RSC
ACTV
*2
t
RRD
*7
1
*7
1
*7
1
*7
1
*6,*7
1
*7
t
RAS
1
READ
*2,*4
1
1
1
*10
1
*10
1
*6
1
*6
1
1
READA
*1,*2
BL+
t
RP
*2,*4
1
*6
1
*6
1
*6,*10
1
*6,*10
1
*6
1
*6
BL+
t
RP
*2
BL+
t
RP
*2,*9
BL+
t
RP
WRIT
*2,*4
1
1
1
1
1
*6
1
*6
t
DPL
1
WRITA
*2
BL-1
+
t
DAL
*2,*4
1
*6
1
*6
1
*6
1
*6
1
*6
1
*6
BL-1
+
t
DAL
*2
BL-1
+
t
DAL
*2
BL-1
+
t
DAL
PRE
*2,*3
t
RP
*2,*4
1
*7
1
*7
1
*7
1
*7
1
*6,*7
1
*7
1
*2
t
RP
*2,*8
t
RP
1
PALL
*3
t
RP
t
RP
1
1
t
RP
*8
t
RP
1
REF
t
RC
t
RC
t
RC
t
RC
t
RC
t
RC
t
RC
SELFX
t
RC
t
RC
t
RC
t
RC
t
RC
t
RC
t
RC
A
R
R
W
W
P
P
R
S
B
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