參數(shù)資料
型號: MB8502D064AA-60
廠商: Fujitsu Limited
英文描述: CMOS 2M×64 BIT Hyper Page Mode DRAM Module(CMOS 2M×64 位超級頁面存取模式動態(tài)RAM模塊)
中文描述: 的CMOS 200萬× 64位超頁模式內(nèi)存的CMOS(200萬× 64位超級頁面存取模式動態(tài)內(nèi)存模塊)
文件頁數(shù): 6/12頁
文件大?。?/td> 157K
代理商: MB8502D064AA-60
6
MB8502D064AA-60/MB8502D064AA-70
I
PIN DESCRIPTIONS
I
PRESENCE DETECT (PD)/ID DEFINITION
I
CAPACITANCE
(T
A
= 25
°
C, f = 1 MHz, V
CC
= +5.0 V)
Min.
Max.
Symbol
Function
Input/Output
Pin Count
A
0
to A
10
, B
0
Address Input
Input
12
RAS0 and RAS2
Row Address Strobe
Input
2
CAS0 to CAS7
Column Address Strobe
Input
8
WE0 and WE2
Write Enable
Input
2
OE0 and OE2
Output Enable
Input
2
DQ
0
to DQ
63
Data-input/Data-output
Input/Output
64
PD
1
to PD
8
Presence Detect
Output
8
ID
0
and ID
1
ID bit
Output
2
PDE
Presence Detect Enable
Input
1
V
CC
Power Supply
16
V
SS
Ground
16
NC
No Connection
35
Symbol
MB8502D064AA-60
MB8502D064AA-70
Description of PD/ID
PD
1
H
H
MODULE DENSITY, DRAM ORGANIZATION AND
ADDRESSING;
Module Density: 16MB, Number of Bank: 1 Bank
Module Configuration: 2M
×
64
Mounted DRAM Configuration: 2M
×
8
DRAM Address (Row/Column): 11/10
PD
2
L
L
PD
3
L
L
PD
4
H
H
PD
5
L
L
EDO DETECTION;
Fast Page Mode : PD
5
= L
PD
6
H
L
MODULE SPEED;
60 ns : PD
6
= H, PD
7
= H
70 ns : PD
6
= L, PD
7
= H
PD
7
H
H
PD
8
H
H
ECC / PARITY DETECTION; (parity) : PD
8
= H
MODULE TYPE;
×
64 (parity) : ID
0
= L
REFRESH MODE; Self Refresh : ID
1
= L
ID
0
L
L
ID
1
H
H
Parameter
Symbol
Unit
Input Capacitance, (Address)
C
IN1
20
pF
Input Capacitance (RAS)
C
IN2
50
pF
Input Capacitance, (CAS, WE, OE)
C
IN3
20
pF
I/O Capacitance, (DQ)
C
DQ
20
pF
相關(guān)PDF資料
PDF描述
MB8502D064AA-70 CMOS 2M×64 BIT Hyper Page Mode DRAM Module(CMOS 2M×64 位超級頁面存取模式動態(tài)RAM模塊)
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MB8502E032AA-70 2 M×32 BITS Hyper Page Mode DRAM Module(CMOS 2 M×32 位超級頁面存取模式動態(tài)RAM模塊)
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