- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄377892 > MB8502E032AA-60 (Fujitsu Limited) 2 M×32 BITS Hyper Page Mode DRAM Module(CMOS 2 M×32 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM模塊) PDF資料下載
參數(shù)資料
| 型號(hào)： | MB8502E032AA-60 |
| 廠商： | Fujitsu Limited |
| 英文描述： | 2 M×32 BITS Hyper Page Mode DRAM Module(CMOS 2 M×32 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM模塊) |
| 中文描述： | 2米× 32位超頁(yè)模式內(nèi)存的CMOS（2米× 32位超級(jí)頁(yè)面存取模式動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 8/10頁(yè) |
| 文件大?。?/td> | 228K |
| 代理商： | MB8502E032AA-60 |
8
MB8502E032AA-60/-70
Notes:
*1. An initial pause (RAS = CAS = V
IH
) of 200
μ
s is required after power-up followed by any eight RAS-
only cycles before proper device operation is achieved. If an internal refresh counter is used, a minimum
of eight CAS -before-RAS initialization cycles are required instead of eight RAS cycles.
*2. AC characteristics assume t
T
= 5 ns.
*3. V
IH
(min) and V
IL
(max) are reference levels for measureing the timing of input signals. Transition times
are measured between V
IH
(min) and V
IL
(max).
*4. Assumes that t
RCD
≤
t
RCD
(max), t
RAD
≤
t
RAD
(max). If t
RCD
is greater than the maximum recommended
value shown in this table, t
RAC
will be increased by the amount that t
RCD
exceeds the value shown.
*5. If t
RCD
≥
t
RCD
(max), t
RAD
≥
t
RAD
(max), and t
ASC
≥
t
AA
- t
CAC
- t
T
, access time is t
CAC
.
*6. If t
RAD
≥
t
RAD
(max) and t
ASC
≤
t
AA
- t
CAC
- t
T
, access time is t
AA
.
*7. Measured with a load equivalent to two TTL loads and 100 pF.
*8. t
OFF
, t
OEZ
, t
OFR
and t
WEZ
are specified that output buffer change to high-impedance state.
*9. Operation within the t
RCD
(max) limit ensures that t
RAC
(max) can be met. t
RCD
(max) is specified as a
reference point only; if t
RCD
is greater than the specified t
RCD
(max) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
*10. t
RCD
(min) = t
RAH
(min)+ 2 t
T
+ t
ASC
(min).
*11. Operation within the t
RAD
(max) limit ensures that t
RAC
(max) can be met. t
RAD
(max) is specified as a
reference point only; if t
RAD
is greater than the specified t
RAD
(max) limit, access time is controlled
exclusively by t
CAC
or t
AA
.
*12. Either t
RRH
or t
RCH
must be satisfied for a read cycle.
*13. t
WCS
is specified as a reference point only. If t
WCS
≥
t
WCS
(min) the data output pin will remain High-Z
state through entire cycle.
*14. Assumes that t
WCS
< t
WCS
(min).
*15. Either t
DZC
or t
DZO
must be satisfied.
*16. t
CPA
is access time from the selection of a new column address (caused by changing CAS from “L” to
“H”). Therefore, if t
CP
become long, t
CPA
also become longer than t
CPA
(max).
*17. Assumes that CAS-before-RAS refresh.
*18. t
WCS
, t
CWD
, t
RWD
, t
AWD
, and t
CPWD
are not restrictive operating parameters. They are included in the data
sheet as an electrical characteristic only. If t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and D
OUT
pin will maintain high-impedance state thoughout the entire cycle. If t
CWD
≥
t
CWD
(min), t
RWD
≥
t
RWD
(min),
t
AWD
≥
t
AWD
(min), and t
CPWD
≥
t
CPWD
(min), the cycle is a read-modify-write cycle and data from the
selected cell will appear at the D
OUT
pin. If neither of the above conditions is satisfied, the cycle is a
delayed write cycle and invalid data will appear the D
OUT
pin, and write operation can be executed by
satisfying t
RWL
, t
CWL
, t
RAL
and t
CAL
specifications.
*19. Assumes that self refresh.
*Source: See MB8118165A Data Sheet for details on the electricals.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB8502E032AA-70 | 2 M×32 BITS Hyper Page Mode DRAM Module(CMOS 2 M×32 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM模塊) |
| MB8502E064AA-60L | 144-PIN SO DIMM 2 M×64 BITS Hyper Page Mode Dram Module(CMOS 2 M×64 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM模塊) |
| MB8502E064AA-70 | 144-PIN SO DIMM 2 M×64 BITS Hyper Page Mode Dram Module(CMOS 2 M×64 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM模塊) |
| MB8502E064AA-70L | 144-PIN SO DIMM 2 M×64 BITS Hyper Page Mode Dram Module(CMOS 2 M×64 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM模塊) |
| MB8502E064AA-60 | 144-PIN SO DIMM 2 M×64 BITS Hyper Page Mode Dram Module(CMOS 2 M×64 位超級(jí)頁(yè)面存取模式動(dòng)態(tài)RAM模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB8508S064CE-100 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8 M x 64 BIT SYNCHRONOUS DYNAMIC RAM SO-DIMM |
| MB85101BAN | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
| MB85101BBN | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
| MB85101CAN | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
| MB85101CBN | 制造商:MURATA 制造商全稱:Murata Manufacturing Co., Ltd. 功能描述:HIGH FREQUENCY CERAMIC CAPACITORS |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。
