參數(shù)資料
型號: MB8502S064AE-84
廠商: Fujitsu Limited
英文描述: CMOS 2M×64Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 2M×64位 同步動態(tài)RAM)
中文描述: 的CMOS 200萬× 64位同步動態(tài)隨機存取存儲器(SDRAM)的CMOS(200萬× 64位同步動態(tài)RAM)的
文件頁數(shù): 1/20頁
文件大?。?/td> 324K
代理商: MB8502S064AE-84
DS05-11116-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
MEMORY
Un-buffered
2 M
×
SYNCHRONOUS DYNAMIC RAM SO DIMM
MB8502S064AE-100/-84/-67
64 BIT
144-pin, 2 Clock, 1-bank, based on 2 M
×
8 BIT SDRAMs with SPD
I
DESCRIPTION
The Fujitsu MB8502S064AE is a fully decoded, CMOS Synchronous Dynamic Random Access Memory (SDRAM)
Module consisting of eight MB81117822A devices which organized as two banks of 2 M
serial EEPROM on a 144-pin glass-epoxy substrate.
The MB8502S064AE features a fully synchronous operation referenced to a positive edge clock whereby all
operations are synchronized at a clock input which enables high performance and simple user interface
coexistence.
The MB8502S064AE is optimized for those applications requiring high speed, high performance and large
memory storage, and high density memory organizations.
This module is ideally suited for workstations, PCs, laser printers, and other applications where a simple interface
is needed.
×
8 bits and a 2 K-bit
I
PRODUCT LINE & FEATURES
Parameter
MB8502S064AE-100
100 MHz max.
10 ns max. (CL = 3)
15 ns max. (CL = 2)
54 ns max.
24 ns max.
8.5 ns max. (CL = 3)
9 ns max. (CL = 2)
3888 mW max.
MB8502S064AE-84
84 MHz max.
12 ns max. (CL = 3)
17 ns max. (CL = 2)
56 ns max.
26 ns max.
8.5 ns max. (CL = 3)
9 ns max. (CL = 2)
3600 mW max.
57.6 mW max.
MB8502S064AE-67
67 MHz max.
15 ns max. (CL = 3)
20 ns max. (CL = 2)
60 ns max.
30 ns max.
9 ns max. (CL = 3)
10 ns max. (CL = 2)
3312 mW max.
Clock Frequency
Burst Mode Cycle Time
RAS Access Time
CAS Access Time
Output Valid from Clock
Power
Dissipation
Burst Mode
Power Down Mode
Unbuffered 144-pin SO-DIMM Socket Type
(Lead pitch: 0.8 mm)
Conformed to JEDEC Standard (2 CLK)
Organization: 2,097,152 words
×
64 bits
Memory: MB81117822A (2 M
×
8, 2-bank)
×
8 pcs.
3.3 V
±
0.3 V Supply Voltage
All input/output LVTTL compatible
2048 Refresh Cycle every 32.8 ms
Auto and Self Refresh
CKE Power Down Mode
DQM Byte Masking (Read/Write)
Serial Presence Detect (SPD) with Serial EEPROM
Module size:
1.0” (height)
×
2.66” (length)
×
0.15” (thick)
相關(guān)PDF資料
PDF描述
MB8502S064AF-100 CMOS 2M×64Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 2M×64位 同步動態(tài)RAM)
MB8502S064AF-67 CMOS 2M×64Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 2M×64位 同步動態(tài)RAM)
MB8502S064AF-84 CMOS 2M×64Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 2M×64位 同步動態(tài)RAM)
MB8502S072AC-100 CMOS 2M×74Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 2M×74位 同步動態(tài)RAM)
MB8502S072AC-67 CMOS 2M×74Bit Synchronous Dynamic Random Access Memory (SDRAM)(CMOS 2M×74位 同步動態(tài)RAM)
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