
FUJITSU LIMITED
PRELIMINARY and CONFIDENTIAL
MB86294/ 294S CORAL_LB
Graphics Controller
Specifications Rev. 1.0
152
DRM (DMA Request Mask)
Register
address
Bit number
Bit field name
R/W
Initial value
HostBaseAddress + 05
H
7
6
5
4
3
2
1
0
Reserved
R0
0
DRM
RW
0
This register enables the DMA request. Setting “1” to this register to temporarily stop the DMA
request from the CORAL. The external request is enabled by setting “0” to this register.
DST (DMA STatus)
Register
address
Bit number
Bit field name
HostBaseAddress + 06
H
7
6
5
4
3
2
1
0
Reserved
R0
0
DST
R
0
R/W
Initial value
This register indicates the DMA transfer status. DST is set to “1” during DMA transfer. This state is
cleared to “0” when the DMA transfer is completed.
DTS (DMA Transfer Stop)
Register
address
Bit number
Bit field name
R/W
Initial value
HostBaseAddress + 08
H
7
6
5
4
3
2
1
0
Reserved
R0
0
DTS
RW
0
This register suspends DMA transfer.
An ongoing DMA transfer is suspended by setting DTS to “1”.
In the dual-address without ACK mode, to end the DMA transfer, write “1” to this register after CPU
DMA transfer.
LTS (display Transfer Stop)
Register
address
Bit number
Bit field name
R/W
Initial value
HostBaseAddress + 09
H
7
6
5
4
3
2
1
0
Reserved
R0
0
LTS
RW
0
This register suspends DisplayList transfer.
Ongoing DisplayList transfer is suspended by setting LTS to “1”.
LSTA (displayList transfer STAtus)
Register
address
Bit number
Bit field name
R/W
Initial value
HostBaseAddress + 10
H
7
6
5
4
3
2
1
0
Reserved
R0
0
LSTA
R
0
This register indicates the DisplayList transfer status from Graphics Memory. LSTA is set to “1” while
DisplayList transfer is in progress. This status is cleared to 0 when DisplayList transfer is completed