參數(shù)資料
型號(hào): MB86602C
廠商: Fujitsu Limited
英文描述: SCSI-II Protocol Controller (Differential)(SCSI-II 協(xié)議控制器)
中文描述: 支持SCSI - II協(xié)議控制器(差異)(支持SCSI - II協(xié)議控制器)
文件頁(yè)數(shù): 6/57頁(yè)
文件大小: 487K
代理商: MB86602C
MB86602C
6
Data bus lower byte and parity bit.
When CS0 is valid, it becomes the SPC internal register input/out-
put port.
When CS1 is valid, it becomes the DMA bus data input/output port.
Address input to select the SPC internal register.
For 80-series Mode, inputs the signal (IORD or RD) for MPU read
from the SPC. Active “L” signal.
For 68-series Mode, inputs the control signal (R/W) for MPU read/
write to the SPC.
Active “H” for read and active “L” for write.
For 80-series Mode, inputs the signal (IOWR or WR) for MPU write
to the SPC.
For 68-series Mode, when the data bus lower byte is valid, inputs
the LDS signal output by the MPU.
Active “L” for both modes.
For 80-series Mode, when the data bus upper byte is valid, inputs
the BHE signal output by the MPU.
For 68-series Mode, when the data bus upper byte is valid, inputs
the UDS signal output by the MPU.
Active “L” for both modes.
Interrupt requests signal output.
Active high for 80-series mode.
Active low for 68-series mode.
2. MPU Interface
Description
Pin
number
I/O
Pin name
Pin
symbol
79
Chip select 0
CS0
I
80
Chip select 1
CS1
I
73, 72, 71,
70, 69, 68,
67, 66
Data 15
to
Data 8
D15
to
D8
I/O
74
Upper data
parity
UDP
The MPU uses this signal to select the SPC as an I/O device.
Active “L” signal.
The MPU uses this selection signal when performing data inputs/
outputs from the DMA bus via the SPC.
Active “L” signal.
Data bus upper byte and parity bit.
When CS0 is valid, it becomes the SPC internal register input/out-
put port.
When CS1 is valid, it becomes the DMA bus data input/output port.
64, 63, 62,
61, 60, 59,
58, 57
Data 7
to
Data 0
D7
to
D0
I/O
56
Lower data
parity
LDP
85, 84, 83,
82, 81
Address 4 to
Address 0
A4 to
A0
I
76
Read
(Read/write)
RD
(R/W)
I
75
Write
(Lower data
strobe)
WR
(LDS)
I
77
Bus high
enable
(Upper data
strobe)
BHE
(UDS)
I
86
Inerrupt
request
INT
(INT)
O
87
Mode
MODE
I
Inputs the signal specifying the type of MPU and DMA buses.
“H” input for 80-series mode.
“L” input for 68-series mode.
*: The pin symbols in parenthesis ( ) are applicable when the MODE input is “L”.
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