
10
MB86605
(Continued)
3.
16-Bit Bus Mode – DMA Interface
(Continued)
Pin no.
Pin name
A4 to A0
I/O
IU These are used to input addresses for selecting the Internal
registers.
I
In 80-series mode: This is used to input the read strobe signal for
reading data from the SPC to the MPU.
In 68-series mode: This is used to input the R/W control signal for
reading and writing data from the MPU to the
SPC.
I
In 80-series mode: This is used to input the write strobe signal for
writing data from the MPU to the SPC.
In 68-series mode: This is used to input the LDS signal output by
the MPU when the lower byte of the data bus
is valid.
I
In 80-series mode: This is used to input the BHE signal output by
the MPU when the upper byte of the data bus
is valid.
In 68-series mode: This is used to input the UDS signal output by
the MPU when the upper byte of the data bus
is valid.
Function
51, 52, 55 to 57
46
RD (R/W)
44
WR (LDS)
42
BHE (UDS)
Pin no.
130
Pin name
DREQ
I/O
O
Function
This is used to output DMA transfer request signals to the DMAC.
DMA data transfer between the SPC and memory is requested.
This is used to input DMA-enabling signals from the DMAC.
When the DMA enabling signal is active, DMA reading and writing
are executed.
I/O Upper byte and parity of DMA data bus
When CS1 input valid: The MPU data bus is directly connected.
When 80-series mode:The 2nd data is input/output.
When 68-series mode:The 1st data is input/output.
I/O Lower byte and parity of DMA data bus
When CS1 input valid: The MPU data bus is directly connected.
When 80-series mode:The 1st data is input/output.
When 68-series mode:The 2nd data is input/output.
I
In 80-series mode:This is used to input the IORD or RD signal for
outputting data from the SPC to the DMA bus.
In 68-series mode:This is used to input the R/W control signal for
outputting and inputting data from the DMAC
to the SPC.
I
In 80-series mode: This is used to input the IOWR or WR signal
for inputting data from the DMA bus to the
SPC.
In 68-series mode: This is used to input the LDS signal output by
the DMAC when the lower byte of the DMA
data bus is valid.
129
DACK
I
138, 139, 141 to 144, 1, 3
136
DMD15 to 8
UDMDP
4, 5, 7, 9 to 11, 13, 14
15
DMD7 to 0
LDMDP
135
DMRD
(DMR/W)
133
DMWR
(DMLDS)