9
MB86605
s PIN DESCRIPTION
1.
SCSI Interface
2.
16-Bit Bus Mode – MPU Interface
(Continued)
Pin no.
Pin name
I/O
Function
84, 81
89, 79
MSG, C/D
ATN, I/O
I/O These are the SCSI control signal input and output pins.
They can be connected directly to a single-ended SCSI connector.
Either open-drain or totem pole output can be selected.
80, 86
REQ, ACK
I/O These are the SCSI control signal input and output pins.
They can be connected directly to a single-ended SCSI connector.
The output buffer is the totem pole type.
68
65
67
BSYOE
SELOE
RSTOE
O These are used for output control of SCSI control signals.
They should be used as control signals for the external differential
driver/receiver circuit.
87
83
85
BSY
SEL
RST
I/O These are the SCSI control signal input and output pins.
They can be connected directly to a single-ended SCSI connector.
The output buffer is the open-drain type.
120, 121, 123, 124, 69 to 72
119
109 to 111, 113 to 115,
117, 118
108
DBOE15 to DBOE8
UDBOEP
DBOE7 to DBOE0
LDBOEP
O These are used for output control of SCSI data bus signals.
They should be used as control signals for the external differential
driver/receiver circuit.
103 to 106, 74 to 76, 78
101
91, 92, 94 to 97, 99, 100
90
DB15 to DB8
UDBP
DB7 to DB0
LDBP
I/O These are used to input and output SCSI data bus signals.
They can be connected directly to a single-ended SCSI connector.
Either open-drain or totem pole output buffer can be selected.
64
62
INIT
TARG
O These are used to output signals indicating the chip operating
status.
They should be used as control signals for the external differential
driver/receiver circuit.
61
S/DSEL
I
This is used to input signal for selecting the chip operation mode.
Single-ended: Input 0
Differential-ended: Input 1
While 0 is input to this pin, all the SCSI control signals, data bus
output control signals, INIT, and TARG signals are fixed with L level.
54
SCLK
I
This pin is used for a system clock input for SCSI protocol
controller block. (Max. 40 MHz)
Pin no.
Pin name
I/O
Function
48
CS0
I
This is used to input signals for the MPU to select the SPC as the
I/O device.
47
CS1
I
This is used to input select signals (external circuit select signals)
for the MPU to input and output the DMA data bus data via the
SPC.
19, 20, 22 to 24, 26 to 28
17
D15 to D8
UDP
I/O Upper byte and parity of data bus
When CS0 input valid: I/O ports for internal registers in SPC
When CS1 input valid: I/O ports for DMA bus data
29, 32 to 34, 36 to 39
41
D7 to D0
LDP
I/O Lower byte and parity of data bus
When CS0 input valid: I/O ports for internal registers in SPC
When CS1 input valid: I/O ports for DMA bus data