參數(shù)資料
型號(hào): MB86612
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 98.304M bps, SERIAL COMM CONTROLLER, PQFP100
封裝: 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 35/35頁
文件大?。?/td> 552K
代理商: MB86612
MB86612
9
OTHERS
Name of pin
I/O
I, I/O
I
O
I
-
O
-
O
X1, X0
VCOIN
CHPO
RESET
MODE0
MODE1
PMODE
PWR1 -
PWR3
BUSRST
TESTP, TESTIO
LINKON
AVDD
AVSS
VDD
VSS
ROP
Function
External crystal oscillator pins for oscillation circuit
VCO input pin for internal PLL
Charge pump output pin for internal PLL
System Reset signal input pin. When no system power is present on the device, input ”0” to this
pin.
MPU Mode select pin. When ”0” : 80-system mode, and when ”1” : 68-system mode
Address/Data multiplexed mode select pin. When ”0”, non- multiplexed mode, and when ”1”:
Multiplexed mode
Power Supply Mode Pin. Input ”L” to this pin when the cable power is activated. Do not set to
”H” until the cable power turns to be OFF or the system power turns to be ON.
Power Class Area Setting Pins for the Cable Powered Mode. The value of POWER_CLASS
area of Self- ID packet is set to these pins. While the device is operating with a System Pow-
ered mode, the value is in accordance with the ’pwr’ bit setting in the Self- ID Setting Register.
Automatic Bus Reset Setting Pin. When ”0” is set to this pin, the device does not perform the
bus reset. When ”1”, it does the bus reset. (When ”1” is set, the device performs the bus reset
after the int- reset bit of flag&status register becomes 1 and then 200ms.)
Test Pins. Do not connect to these pins.
Link- on Packet detection pin. At the receipt of link- on packet, this pin outputs ”H” signal for 1 to
2 tCLK time (i.e., 1 to 2 cycles of crystal oscillation input.) When this signal is not used, please
leave this pin open.
Analog power supply pin
Analog GND pin
Digital power supply pin
Digital GND pin
Ground this pin with a 4.7kW resistor.
相關(guān)PDF資料
PDF描述
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