參數(shù)資料
型號(hào)： MB86831PFV
廠(chǎng)商： FUJITSU LTD
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-bit Embedded Controller
中文描述： 32-BIT, RISC MICROCONTROLLER, PQFP176
封裝： 24 X 24 MM, PLASTIC, QFP-176
文件頁(yè)數(shù)： 61/82頁(yè)
文件大?。?/td> 1373K
代理商： MB86831PFV
MB86830 Series
61
controller also controls the RAS and CAS to place DRAM in the self-refresh mode when the processor enters the
sleep mode (low power consumption mode).
The MB86836 has no DRAM controller.
10. Interrupt Controller (IRC)
The interrupt controller (IRC) accepts interrupts inputs through eight channels, depending on the trigger mode and
mask bit set for each of the channels. When accepting an interrupt, the interrupt controller encodes it according
to the interrupt priority level and outputs the interrupt level to the processor. The interrupt level remains held unless
it is cleared by the processor. The processor is not therefore informed of the next interrupt.
11. Multiplier Circuit
The CLKSEL0, CLKSEL1, and CLKSEL2 pins can be used to select the multiplier circuit to be used. The
×
1,
×
2,
×
3,
×
4, or
×
5 multiplier circuits are supported, which allow the processor to run faster.
12. IU (Integer Unit) Dedicated Registers (Not Memory Mapped)
(1)Processor Status Register (PSR)
bit
→
31
28 27
bit 23 to bit 20 :Integer condition code [icc] (n:Negative
=
1, z:Zero
=
1, v:Overflow
=
1, c:Carry
=
1)
bit 19 to bit 12 :Reserved[“0”Write, Don’t care for read]
bit 11 to bit 8
:Processor Interrupt Level [PIL] (Value
=
1 to 15, RST
=
X)
bit 7
:Supervisor Mode [S] (Supervisor
=
1, User
=
0, RST
=
1)
bit 6
:Prior S Mode [PS]
bit 5
:Enable Trap [ET] (Enable
=
1, Disable
=
0, RST
=
0)
bit 4 to bit 3
:Reserved [“0”Write, Don’t care for read]
bit 2 to bit 0
:Current Window Point [CWP] (Value
=
0 to 7, RST
=
X)
X:Don’t care
(2)Window Invalid Mask Register (WIM)
bit
→
31
bit 31 to bit 8
bit 7 to bit 0
:Reserved [“0”Write, Don’t care for read]
:Window mask [w7 to w0] (Invalid
=
1, Valid
=
0, RST
=
X)
X:Don’t care
(3)Trap Base Register (TBR)
bit
→
31
bit 31 to bit 12 :Trap base address [TBA] (RST
=
X)
bit 11 to bit 4
:Trap type [tt] (RST
=
X)
X:Don’t care
24 23
20 19
12 11
8
7
6
5
4
3
2
0
0 0 0 0
H
1 1 1 1
H
icc
Reserved
PIL
S
PS ET Reserved
CWP
n
z
v
c
8
7
6
5
4
3
2
1
0
Reserved
w7 w6 w5 w4 w3 w2 w1 w0
12 11
4
3
0
TBA
tt
0 0 0 0
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