SPARClite Series 32-Bit RISC Embedded Processor
4
Fujitsu Microelectronics, Inc.
Idle Cycle Insertion Function ......................................................................................................................................... 22
IDLEEN Pin Tied Low ........................................................................................................................................... 22
IDLEEN Pin Tied High .......................................................................................................................................... 22
Idle Cycle Insertion Function ......................................................................................................................................... 23
MB86832 Control and Status Registers—Read/Write ...................................................................................................... 24
MB86832 Memory Mapped Control Registers—Read/Write ............................................................................................. 25
Bus Operation .................................................................................................................................................................... 31
Operation of the BIU ................................................................................................................................................... 31
Exception Handling ............................................................................................................................................... 31
Bus Cycles ............................................................................................................................................................. 31
Load .................................................................................................................................................................... 31
Load (32-bit bus width).......................................................................................................................................... 31
Load (16-bit bus width).......................................................................................................................................... 32
Load (8-bit wide bus) ............................................................................................................................................. 32
Load with Exception .............................................................................................................................................. 32
Store .................................................................................................................................................................... 32
Store (32-bit bus width).......................................................................................................................................... 32
Store (16-bit wide bus) ........................................................................................................................................... 32
Store (8-bit wide bus) ............................................................................................................................................. 32
Store with Exception .............................................................................................................................................. 32
Atomic Load Store ................................................................................................................................................. 32
External Bus Request and Grant .............................................................................................................................. 32
8- and 16-Bit Bus Modes ......................................................................................................................................... 33
Bus Width Control of -CS0 ........................................................................................................................................... 33
Bus Width Control Bits of -CS1 to -CS5 ......................................................................................................................... 33
Burst Mode Transactions ......................................................................................................................................... 33
ADR<3:2> Sequence in Burst Mode .............................................................................................................................. 33
Selection of Hyperpage Mode (EDO Mode)............................................................................................................... 33
Basic DRAM Access Timing ........................................................................................................................................... 34
DRAM Access Timing ................................................................................................................................................... 34
Electrical Characteristics ..................................................................................................................................................... 46
Absolute Maximum Ratings ........................................................................................................................................... 46
Recommended Operating Conditions .............................................................................................................................. 46
DC Characteristics ....................................................................................................................................................... 47
AC Characteristics ....................................................................................................................................................... 48
Exterior Package Drawing ............................................................................................................................................ 52