![](http://datasheet.mmic.net.cn/330000/MB86831_datasheet_16436326/MB86831_71.png)
MB86830 Series
71
(6)IRL Latch/Clear Register (IRLAT)
CS3#
=
L, Address<9:2>
=
0x05
bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 5
:Reserved [“0”Write, Read"0"]
bit 4
:IRL Clear [Wite only] (Clear
=
1, Not Clear
=
0)
bit 3 to bit 0
:IRL Latch [Read only] (RST
=
0000)
(7)IRC Mode Register (IMODE)
CS3#
=
L, Address<9:2>
=
0x06
bit 31 to bit 16 :Reserved [“0”Write, Don’t care for read]
bit 15 to bit 2
:Reserved [“0”Write, Read“0”]
bit 1 to bit 0
:IRC Mode [IRCMD] (Disable
=
00, Enable
=
01, RST
=
00)
17. DRAM controller
(1)DRAM Bank Configuration Register (DBANKR)
CS3#
=
L, Address<9:2>
=
0x08
bit 31
bit 30 to bit 11 :Reserved [“0”Write, Don’t care for read]
bit 10 to bit 9
:DRAM Start Address [STADR] (RST
=
01)
bit 8
:Hyper Page Enable [HE] (Page Mode DRAM
=
0, EDO DRAM
=
1, RST
=
0)
bit 7
:DRAM Type[TP] (4CAS-1WE= 0, 4WE -1CAS
=
1, RST
=
0)
bit 6 to bit 4
:Column Address [COL] (RST
=
011)
bit 3 to bit 0
:Bank Size [BKSIZE] (RST
=
0011)
:Access Error [ERR] (Error
=
1, No Error
=
0, RST
=
X, “0”Write Clear)
X:Don’t care
(2)DRAM Timing Register (DTIMR)
CS3#
=
L, Address<9:2>
=
0x09
bit 31 to bit 5
bit 4
bit 3 to bit 2
:Reserved [“0”Write, Don’t care for read]
:RAS#Precharge time specification bits [T
RPS
] at Self-Refresh
(2 Cycle
=
0, 4 Cycle
=
1, RST
=
1)
:RAS#Pulse width specification bit [T
RASCBR
] at CBR Refresh
(1 Cycle
=
00, 2 Cycle
=
01, 3 Cycle
=
10, RST
=
01)
:CAS#Pulse width specification bit [T
CAS
] (1 Cycle
=
0, 2 Cycle
=
1, RST
=
1)
:RAS#Precharge width specification bit [T
RP
] (1 Cycle
=
0, 2 Cycle
=
1, RST
=
0)
bit 1
bit 0
bit
→
31
16 15
5
4
3
0
Reserved
Reserved
CL
IRL
bit
→
31
16 15
2
1
0
Reserved
Reserved
IRCMD
bit
→
31
11 10
9
8
7
6
4
3
0
ERR
Reserved
STADR
HE TP
COL
BKSIZE
bit
→
31
5
4
3
2
1
0
Reserved
T
RPS
T
RASCBR
T
CAS
T
RP