參數(shù)資料
型號(hào): MB86961A
廠商: Fujitsu Limited
英文描述: UNIVERSAL INTERFACE FOR 10BASET
中文描述: 通用接口10BASET
文件頁數(shù): 18/29頁
文件大?。?/td> 292K
代理商: MB86961A
MB86961A
18
Table 7.
RCLK/Start-of-Packet Timing
Note:
Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
Table 8.
RCLK/End-of-Packet Timing
Notes: 1. Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
2. CD Turn off delay measured from middle of last bit, so timing specification is unaffected by the value of the
last bit.
Table 9.
Transmit Timing
Note:
Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
Table 10.
Collision Detection, COL/CI Output and Loopback Timing
Note:
Typical figures are at 25
°
C and are for design aid only; not guaranteed and not subject to production testing.
Symbol
Parameter
Min.
Typ.
1
Max.
Units
t
DATA
Decoder acquisition time
AUI
900
ns
TP
1300
ns
t
CD
CD turn-on delay
AUI
50
ns
TP
400
ns
t
RDS
Receive data setup from RCLK
Mode 1
40
ns
Modes 2, 3 and 4
30
ns
t
RDH
Receive data hold from RCLK
Mode 1
10
ns
Modes 2, 3 and 4
30
ns
Symbol
Parameter
Type
Mode 1
Mode 2
Mode 3
Mode 4
Units
t
RCH
RCLK hold after CD low
Min.
0
1
27
5
bt
t
RD
RCV data throughput delay
Typ.
300
275
275
275
ns
t
CDOFF
CD turn off delay
Typ.
400
375
375
375
ns
t
IFG
Receive block out
Typ.
2
50
27
5
bt
Symbol
Parameter
Min.
Typ.
1
Max.
Units
t
EHCH
TEN setup from TCLK
30
ns
t
DSCH
TXD setup from TCLK
30
ns
t
CHEL
TEN hold after TCLK
5
ns
t
CHDU
TXD hold after TCLK
5
ns
Symbol
Parameter
Min.
Typ.
1
Max.
Units
t
COLD
COL turn on delay
50
ns
t
COLOFF
COL turn off delay
160
ns
t
SQED
SQE Delay
0.65
1.6
m
s
t
SQEP
SQE Pulse Duration
500
1500
ns
t
KHEH
LBK setup from TEN
25
ns
t
KHEL
LBK hold after TEN
0
ns
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