參數(shù)資料
型號(hào)： MB88151APNF-G-401-JNERE1
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： OTHER CLOCK GENERATOR, PDSO8
封裝： 3.90 X 5.05 MM, 1.75 MM HEIGHT, 1.27 MM PITCH, SOP-8
文件頁(yè)數(shù)： 7/24頁(yè)
文件大小： 686K
代理商： MB88151APNF-G-401-JNERE1
MB88151A
DS04-29127-2E
15
■ LOCK-UP TIME
If the setting pin is fixed at the “H” or “L” level, the maximum time after the power is turned on until the set clock
signal is output from CKOUT pin is (the stabilization wait time of input clock to XIN pin)
+ (the lock-up time “tLK”).
For the input clock stabilization time, check the characteristics of the resonator or oscillator used.
For modulation enable control using the ENS pin during normal operation, the set clock signal is output from
CKOUT pin at most the lock-up time (tLK) after the level at the ENS pin is determined.
Note : When the pin setting is changed, the CKOUT pin output clock stabilization time is required. Until the output
clock signal becomes stable, the output frequency, output clock duty cycle, modulation period, and cycle-
cycle jitter cannot be guaranteed. It is therefore advisable to perform processing such as cancelling a reset
of the device at the succeeding stage after the lock-up time.
3.0 V
VDD
XIN
VIH
CKOUT
Setting pin
SEL0,
SEL1,
ENS
Internal clock
stabilization wait time
tLK
(lock-up time )
VIL
VIH
XIN
ENS
CKOUT
tLK
(lock-up time )
tLK
(lock-up time )
相關(guān)PDF資料
PDF描述
MB88151APNF-G-100-JNERE1 OTHER CLOCK GENERATOR, PDSO8
MB88151PNF-G-200-JN-EFE1 66.7 MHz, OTHER CLOCK GENERATOR, PDSO8
MB88151PNF-G-200-JNE1 66.7 MHz, OTHER CLOCK GENERATOR, PDSO8
MB88151PNF-G-400-JNE1 133.4 MHz, OTHER CLOCK GENERATOR, PDSO8
MB88151PNF-G-400-JN-ERE1 133.4 MHz, OTHER CLOCK GENERATOR, PDSO8
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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