參數(shù)資料
型號: MB88152PNF-G-112-JN-ERE1
廠商: FUJITSU LTD
元件分類: 時鐘產(chǎn)生/分配
英文描述: 134 MHz, OTHER CLOCK GENERATOR, PDSO8
封裝: PLASTIC, SOP-8
文件頁數(shù): 6/20頁
文件大?。?/td> 178K
代理商: MB88152PNF-G-112-JN-ERE1
MB88152
14
■ LOCK-UP TIME
If the setting pin is fixed at the “H” or “L” level, the maximum time after the power is turned on until the set clock
signal is output from CKOUT pin is (the stabilization wait time of input clock to XIN pin)
+ (the lock-up time “tLK”).
For the input clock stabilization time, check the characteristics of the resonator or oscillator used.
For modulation enable control using the XENS pin during normal operation, the set clock signal is output from
CKOUT pin at most the lock-up time (tLK) after the level at the XENS pin is determined.
Note : When the pin setting is changed, the CKOUT pin output clock stabilization time is required. Until the output
clock signal becomes stable, the output frequency, output clock duty cycle, modulation period, and cycle-
cycle jitter cannot be guaranteed. It is therefore advisable to perform processing such as cancelling a reset
of the device at the succeeding stage after the lock-up time.
3.0 V
VDD
XIN
Setting pin
SEL
FREQ1/XENS
FREQ0/FREQ
VIH
CKOUT
Internal clock
stabilization wait time
tLK
(lock-up time )
VIH
VIL
XIN
XENS
CKOUT
tLK
(lock-up time )
tLK
(lock-up time )
相關PDF資料
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