參數(shù)資料
型號(hào): MB88153APNF-G-101-JNE1
廠商: FUJITSU LTD
元件分類: 時(shí)鐘及定時(shí)
英文描述: 88153 SERIES, PLL BASED CLOCK DRIVER, 1 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封裝: 3.90 X 5.05 MM, 1.27 MM PITCH, 1.75 MM HEIGHT, PLASTIC, SOP-8
文件頁(yè)數(shù): 22/24頁(yè)
文件大?。?/td> 230K
代理商: MB88153APNF-G-101-JNE1
MB88153A
7
■ PIN SETTING
When changing the pin setting, the stabilization wait time for the modulation clock required. The stabilization
wait time for the modulation clock takes the maximum value of Lock-Up time in “■ ELECTRICAL CHARACTER-
ISTICS
AC Characteristics”.
ENS modulation enable setting
Note : Spectrum does not spread when “L” is set to ENS. The clock with low jitter can be obtained.
FREQ0, FREQ1 frequency setting
Note : It is set according to the frequency of the clock input to the device. Set FREQ0 pin to “H” for the pin opened
because FREQ0 pin has pull-up resistor.
XPD power down setting
Note : When “L” is set to XPD pin, the power down operation is implemented and “L” is output to CKOUT pin. When
“H” is input to XPD pin or XPD pin is opened, normal operation is implemented because the XPD pin has
pull-up resistor.
ENS
Modulation
L
No modulation
H
Modulation
FREQ0
FREQ1
Input frequency range
L
16.6 MHz to 40 MHz
L
H
66 MHz to 134 MHz
H
L
33 MHz to 67 MHz
H
40 MHz to 80 MHz
XPD
Power down
L
Power down
H
Normal operation
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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