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參數(shù)資料
| 型號： | MB881821BPVA1-G-EFE1 |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PBCC20 |
| 封裝： | 3.50 X 3.50 MM, 0.60 MM HEIGHT, 0.50 MM PITCH, PLASTIC, BCC-20 |
| 文件頁數(shù)： | 18/32頁 |
| 文件大?。?/td> | 919K |
| 代理商： | MB881821BPVA1-G-EFE1 |
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MB88182
DS04-29138-1E
25
<Output timing with XPDREF control>
<Lock-up time>
If the power down control is performed on pins XPD1, XPD2, XPD3 and XPD4, the desired clock frequency will
be obtained once the power down pin becomes at the “H” level and after the lock-up time tLK has passed at
maximum.
If the ENS pin setting changes during the normal operation, setting clocks CLK2, CLK3 and CLK4 will be output
once the ENS pin level is decided and after lock-up time tLK has passed at maximum.
Note: When the ENS pin setting is changed, the stabilization wait time is needed for the output clock from CLK2,
CLK3 and CLK4 pins. During the stabilization wait time, the output frequency, output clock duty cycle,
modulation frequency, and cycle-cycle jitter cannot be guaranteed. It is therefore advisable to perform pro-
cessing such as cancelling a reset of the device at the succeeding stage after the lock-up time.
XPDREF
CKREF
XPDREF
CKREF
VIL
VIH
tP
tRPD
tROE
CLK1, CLK2,
CLK3, CLK4
CKIN
XPD1, XPD2,
XPD3, XPD4
VIH
VIL
tLK (lock-up time)
CLK2,
CLK3,CLK4
CKIN
ENS
VIH
VIL
tLK
(lock-up time)
tLK
(lock-up time)
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