參數(shù)資料
型號: MB881822BPVA1-G-EFE1
廠商: FUJITSU LTD
元件分類: 時鐘產(chǎn)生/分配
英文描述: 100 MHz, OTHER CLOCK GENERATOR, PBCC20
封裝: 3.50 X 3.50 MM, 0.60 MM HEIGHT, 0.50 MM PITCH, PLASTIC, BCC-20
文件頁數(shù): 4/36頁
文件大?。?/td> 1059K
代理商: MB881822BPVA1-G-EFE1
MB88182
12
DS04-29138-3E
■ SETTING REGISTER
<Memory map>
Setting register for CLK2, CLK3, CLK4 (All registers have the same configurations.)
CLK1 setting register
Note: The bit's initial value in a register is undefined. Therefore, if the power down of clock output is released before
the register setting, the clock is output with settings unintended. The power down of the clock output for
CLK1, CLK2, CLK3 and CLK4 should be released after setting to registers.
Address
Function
Remarks
bit0 to 11
M divider setting (12-bit)
Selectable in the range of 100 to 3600
bit12 to 22
N divider setting (11-bit)
Selectable in the range of 3 to 2047
bit23 to 27
K divider setting (5-bit)
Selectable in the range of 1 to 32
bit28 to 30
L divider setting (3-bit)
Modulation frequency setting (selectable in the range of 1 to 8)
bit31 to 34
Charge Pump setting (4-bit)
Charge pump current setting due to internal oscillation frequency
and M divider setting
bit35 to 40
VCO Gain setting (6-bit)
Gain setting due to internal oscillation frequency
bit41 to 43
Modulation rate setting
(3-bit)
modulation off,
± 0.25%, ± 0.50%, ± 0.75%, ± 1.00%,
± 1.25%, ± 1.50%, ± 1.75% are selectable
bit44
Output drive setting
0 : Ability small, 1 : Ability large
bit45
Slewing rate setting
0 : Slewing rate low, 1 : Slewing rate high
bit46, 47
Invalid bit
When in writing : The written data is ignored.
When in reading : Undefined
Address
Function
Remarks
bit0 to 5
M divider setting (6-bit)
Selectable in the range of 3 to 52
bit6 to 10
N divider setting (5-bit)
Selectable in the range of 3 to 31
bit11 to 15
K divider setting (5-bit)
Selectable in the range of 1 to 32
bit16 to 19
Charge Pump setting (4-bit)
Charge pump current setting due to internal oscillation frequency
and M divider setting
bit20 to 25
VCO Gain setting (6-bit)
Gain setting due to internal oscillation frequency
bit26
Output drive setting
0 : Ability small, 1 : Ability large
bit27
Slewing rate setting
0 : Slewing rate low, 1 : Slewing rate high
bit28 to 31
Invalid bit
When in writing : The written data is ignored.
When in reading : Undefined
相關(guān)PDF資料
PDF描述
MB881821APVA1-G-ERE1 100 MHz, OTHER CLOCK GENERATOR, PBCC20
MB881821BPVA1-G-ERE1 100 MHz, OTHER CLOCK GENERATOR, PBCC20
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MB881821BPVA1-G-EFE1 100 MHz, OTHER CLOCK GENERATOR, PBCC20
MB881822APVA1-G-EFE1 100 MHz, OTHER CLOCK GENERATOR, PBCC20
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