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參數(shù)資料
| 型號： | MB89530A |
| 廠商： | Fujitsu Limited |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-BIT MICROCONTROLLER |
| 中文描述： | 8位微控制器 |
| 文件頁數(shù)： | 47/69頁 |
| 文件大?。?/td> | 1206K |
| 代理商： | MB89530A |
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MB89530A Series
47
(7) I
2
C Timing
(V
CC
=
5.0 V, AVss
=
Vss
=
0 V, T
A
=
40
°
C to
+
85
°
C)
Value
Notes :
For t
inst
refer to “ (4) Instruction Cycle”.
The value “m” in the above table is the value from the shift clock frequency setting bits (CS4, CS3) in the
I
2
C clock control register “ICCR”. For details, refer to the register description in the hardware manual.
The value ’n’ in the above table is the value from the shift clock frequency setting bits (CS2, CS0) in the
I
2
C clock control register “ICCR”. For details, refer to the register description in the hardware manual.
t
DOSU
appears when the interrupt period is longer than the SCL “L” width.
The rated values for SDA and SCL assume a start up time of 0 ns.
Parameter
Symbol
Pin
name
Condition
Unit Remarks
Min
Max
Start condition output
t
STA
SCL
SDA
1
/
4 t
inst
×
m
×
n
20
1
/
4 t
inst
×
(m
×
n
+
8)
20
1
/
4 t
inst
×
m
×
n
+
20
1
/
4 t
inst
×
(m
×
n
+
8)
+
20
ns
Master
only
Stop condition output
t
STO
SCL
SDA
ns
Master
only
Start condition detection
t
STA
SCL
SDA
1
/
4 t
inst
×
6
+
40
ns
Stop condition detection
t
STO
SCL
SDA
1
/
4 t
inst
×
6
+
40
ns
Restart condition output
t
STASU
SCL
SDA
1
/
4 t
inst
×
(m
×
n
+
8)
20
1
/
4 t
inst
×
(m
×
n
+
8)
+
20
ns
Master
only
Restart condition detection
t
STASU
SCL
SDA
1
/
4 t
inst
×
4
+
40
ns
SCL output “L” width
t
LOW
SCL
1
/
4 t
inst
×
m
×
n
20
1
/
4 t
inst
×
(m
×
n
+
8)
20
1
/
4 t
inst
×
4
20 1
/
4 t
inst
×
4
+
20
1
/
4 t
inst
×
m
×
n
+
20
1
/
4 t
inst
×
(m
×
n
+
8)
+
20
ns
Master
only
SCL output “H” width
t
HIGH
SCL
ns
Master
only
SDA output delay time
t
DO
SDA
ns
Setup after SDA output
interrupt interval
t
DOSU
SDA
1
/
4 t
inst
×
4
20
ns
SCL input “L” width
t
LOW
SCL
1
/
4 t
inst
×
6
+
40
1
/
4 t
inst
×
2
+
40
40
ns
SCL input “H” width
t
HIGH
SCL
ns
SDA input setup
t
SU
SDA
ns
SDA input hold
t
HO
SDA
0
ns
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