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參數(shù)資料
| 型號： | MB89623RPFV |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit Proprietary Microcontroller |
| 中文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 26/61頁 |
| 文件大?。?/td> | 915K |
| 代理商： | MB89623RPFV |
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26
MB89620R Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag:Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
to ‘0’ otherwise. This flag is for decimal adjustment instructions.
I-flag: Interrupt is enabled when this flag is set to ‘1’. Interrupt is disabled when the flag is cleared to ‘0’. Cleared
to ‘0’ at the reset.
IL1, 0:Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
N-flag:Set to ‘1’ if the MSB becomes ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit is
cleared to ‘0’.
Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise.
V-flag: Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to ‘0’ if the
overflow does not occur.
C-flag:Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to ‘0’
otherwise.
Set to the shift-out value in the case of a shift instruction.
Interrupt level
High-low
0
0
1
High
Low
0
1
1
0
2
1
1
3
Rule for Conversion of Actual Addresses of the General-purpose Register Area
“0”
↓
A15
“0”
↓
A14
“0”
↓
A13
“0”
↓
A12
“0”
↓
A11
“0”
↓
A10
“0”
↓
A9
“1”
↓
A8
R4
↓
A7
R3
↓
A6
R2
↓
A5
R1
↓
A4
R0
↓
A3
b2
↓
A2
b1
↓
A1
b0
↓
A0
Lower OP codes
RP
Generated addresses
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB89625R | Octal Buffers/Drivers With 3-State Outputs 20-CDIP -55 to 125 |
| MB89626RP-SH | Octal Transparent D-type Latches With 3-State Outputs 20-CDIP -55 to 125 |
| MB89626RPF | Octal Transparent D-type Latches With 3-State Outputs 20-CFP -55 to 125 |
| MB89626RPFM | Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs 20-LCCC -55 to 125 |
| MB89627R | Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs 20-CDIP -55 to 125 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB89623RP-SH | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89625 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89625PF | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89625PFM | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89625PFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
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