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參數(shù)資料
| 型號(hào)： | MB89626RPFM |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Octal Edge-Triggered D-type Flip-Flops With 3-State Outputs 20-LCCC -55 to 125 |
| 中文描述： | 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 37/61頁(yè) |
| 文件大?。?/td> | 915K |
| 代理商： | MB89626RPFM |
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37
MB89620R Series
(6) Bus Read Timing
(V
CC
= +5.0 V
±
10%, F
C
= 10 MHz, AV
SS
= V
SS
= 0.0 V, T
A
= –40
°
C to +85
°
C)
Value
*: For information on t
inst
, see “(4) Instruction Cycle.”
Parameter
Symbol
Pin name
Condition
Unit Remarks
Min.
Max.
Valid address
→
RD
↓
time
t
AVRL
RD, A15 to A08,
AD7 to AD0
—
1/4 t
inst
*– 64 ns
—
μ
s
RD pulse width
t
RLRH
RD
1/4 t
inst
*– 20 ns
—
μ
s
Valid address
→
data read time
t
AVDV
AD7 to AD0,
A15 to A08
—
1/2 t
inst
*
μ
s
In the case
of no wait
RD
↓
→
data read time
t
RLDV
RD, AD7 to AD0
—
1/2 t
inst
*– 80
ns
μ
s
In the case
of no wait
RD
↑ →
data hold time
RD
↑ →
ALE
↑
time
RD
↑ →
address invalid time
RD
↓ →
CLK
↑
time
CLK
↓
→
RD
↑
time
RD
↓ →
BUFC
↓
time
t
RHDX
AD7 to AD0, RD
0
—
μ
s
μ
s
μ
s
μ
s
ns
μ
s
t
RHLH
RD, ALE
1/4 t
inst
*– 40 ns
—
t
RHAX
RD, A15 to A08
1/4 t
inst
*– 40 ns
—
t
RLCH
RD, CLK
1/4 t
inst
*– 40 ns
—
t
CLRH
0
—
t
RLBL
RD, BUFC
–5
—
BUFC
↑
→
valid address time t
BHAV
A15 to A08,
AD7 to AD0,
BUFC
5
—
μ
s
ALE
AD
A
RD
BUFC
CLK
2.4 V
0.8 V
0.8 V
2.4 V
0.8 V
0.7 V
CC
0.3 V
CC
0.7 V
CC
0.3 V
CC
2.4 V
0.8 V
2.4 V
0.8 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
2.4 V
0.8 V
t
RHDX
t
BHAV
t
RLBL
t
CLRH
t
RHL
t
AVD
t
AVRL
t
RLC
t
RLR
t
RHA
t
RLDV
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| MB89627P-SH | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
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