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參數(shù)資料
| 型號： | MB89665 |
| 廠商： | Fujitsu Limited |
| 英文描述： | Quadruple Bus Buffer Gates With 3-State Outputs 14-CDIP -55 to 125 |
| 中文描述： | 8位微控制器專有 |
| 文件頁數(shù)： | 19/48頁 |
| 文件大?。?/td> | 652K |
| 代理商： | MB89665 |
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MB89660 Series
19
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag:
Set when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
otherwise. This flag is for decimal adjustment instructions.
I-flag:
Interrupt is allowed when this flag is set to 1. Interrupt is prohibited when the flag is set to 0. Set to 0
when reset.
IL1, 0:
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
N-flag:
Set if the MSB is set to 1 as the result of an arithmetic operation. Cleared when the bit is set to 0.
Z-flag:
Set when an arithmetic operation results in 0. Cleared otherwise.
V-flag:
Set if the complement on 2 overflows as a result of an arithmetic operation. Reset if the overflow does
not occur.
C-flag:
Set when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared otherwise.
Set to the shift-out value in the case of a shift instruction.
IL1
IL0
Interrupt level
High-low
0
0
1
High
Low = no interrupt
0
1
1
0
2
1
1
3
Rule for Conversion of Actual Addresses of the General-purpose Register Area
“0”
↓
A15
“0”
↓
A14
“0”
↓
A13
“0”
↓
A12
“0”
↓
A11
“0”
↓
A10
“0”
↓
A9
“1”
↓
A8
R4
↓
A7
R3
↓
A6
R2
↓
A5
R1
↓
A4
R0
↓
A3
b2
↓
A2
b1
↓
A1
b0
↓
A0
Lower OP codes
RP
Generated addresses
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB89665P-SH | Quadruple Bus Buffer Gates With 3-State Outputs 14-CFP -55 to 125 |
| MB89665PF | Quadruple Bus Buffer Gates With 3-State Outputs 20-LCCC -55 to 125 |
| MB89P665 | 0.22A, 2.7-5.5V Single Power Distribution Switch IC Hi-Side MOSFET, Fault Report, Act-Low Enable 8-SOIC |
| MB89P665P-SH | 8-bit Proprietary Microcontroller |
| MB89P665PF | 0.22A, 2.7-5.5V Single Power Distribution Switch IC Hi-Side MOSFET, Fault Report, Act-Low Enable 8-PDIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB89665PF | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89665P-SH | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89665R | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89665RPF | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89665RP-SH | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
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