參數(shù)資料
型號: MB89665R
廠商: Fujitsu Limited
英文描述: Quadruple Bus Buffer Gates With 3-State Outputs 14-CDIP -55 to 125
中文描述: 8位微控制器專有
文件頁數(shù): 17/47頁
文件大?。?/td> 649K
代理商: MB89665R
17
MB89660R Series
I
CPU CORE
1. Memory Space
The microcontrollers of the MB89660R series offer 64 Kbytes of memory for storing all of I/O, data, and program
areas. The I/O area is allocated from the lowest address. The data area is allocated immediately above the I/O
area. The data area can be divided into register, stack, and direct areas according to the application. The program
area is allocated from exactly the opposite end, that is, near the highest address. The tables of interrupt reset
vectors and vector call instructions are allocated from the highest address within the program area. The memory
space of the MB89660R series is structured as illustrated below.
Memory Space
0000
H
0080
H
0100
H
0180
H
E000
H
FFFF
H
MB89663R
I/O
RAM
256 B
Register
0000
H
0080
H
0100
H
0200
H
C000
H
FFFF
H
MB89665R
MB89W665
MB89P665
I/O
RAM
512 B
Register
ROM*
16 KB
Not available
Not available
0280
H
*: When the MB89P665 is used for evaluation, the internal ROM cannot be used.
ROM
8 KB
相關(guān)PDF資料
PDF描述
MB89665RP-SH Quadruple Bus Buffer Gates With 3-State Outputs 14-CFP -55 to 125
MB89665RPF 3-Line To 8-Line Decoders/Demultiplexers 20-LCCC -55 to 125
MB89663 Quadruple Bus Buffer Gates With 3- State Outputs 20-LCCC -55 to 125
MB89663P-SH Quadruple Bus Buffer Gates With 3- State Outputs 14-CDIP -55 to 125
MB89663PF Quadruple Bus Buffer Gates With 3- State Outputs 14-CFP -55 to 125
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