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參數(shù)資料
| 型號： | MB89935A |
| 廠商： | Fujitsu Limited |
| 英文描述： | Hex Schmitt-trigger Inverters 14-CFP -55 to 125 |
| 中文描述： | 8位微控制器專有 |
| 文件頁數(shù)： | 17/46頁 |
| 文件大小： | 633K |
| 代理商： | MB89935A |
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MB89930A Series
17
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.
Cleared to “0” otherwise. This flag is for decimal adjustment instructions.
I-flag :
Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when the flag is cleared to “0”.
Cleared to “0” at the reset.
IL1, 0 :
Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
IL0
Interrupt level
High-low
0
0
1
High
Low
=
no interrupt
0
1
1
0
2
1
1
3
N-flag : Set to “1” if the MSB becomes to “1” as the result of an arithmetic operation. Cleared to “0” when the
bit is cleared to “0”.
Z-flag : Set to “1” when an arithmetic operation results in 0. Cleared otherwise.
V-flag : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0” if the
overflow does not occur.
C-flag : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to
“0” otherwise. Set to the shift-out value in the case of a shift instruction.
"0"
"0"
"0"
"0"
"0"
"0"
"0"
"1"
R4
R3
R2
R1
R0
b2
b1
RP
Low OP codes
b0
A7
A6
A5
A4
A3
A2
A1
A0
A15
Generated addresses
A14 A13 A12 A11 A10
A9
A8
Rule for Conversion of Actual Addresses of the General-purpose Register Area
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MB89935APFV | Quadruple 2-Line To 1-Line Data Selectors/Multiplexers 20-LCCC -55 to 125 |
| MB89935B | Quadruple 2-Line To 1-Line Data Selectors/Multiplexers 16-CDIP -55 to 125 |
| MB89935BPFV | Quadruple 2-Line To 1-Line Data Selectors/Multiplexers 16-CFP -55 to 125 |
| MB89PV930A | 8-bit Proprietary Microcontroller |
| MB89PV930ACFV | 8-bit Proprietary Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB89935APFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89935B | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89935BPFV | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB8993X | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontroller |
| MB89940 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontrolle |
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