參數(shù)資料
型號(hào): MB89F202RAP-SH
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 12.5 MHz, MICROCONTROLLER, PDIP32
封裝: 1.778 MM PITCH, PLASTIC, DIP-32
文件頁數(shù): 23/48頁
文件大?。?/td> 1266K
代理商: MB89F202RAP-SH
MB89202R Series
DS07-12562-3E
3
■ PRODUCT LINEUP
(Continued)
Part number
MB89202
MB89202Y
MB89F202RA
MB89F202RAY
MB89V201
Parameter
Classification
Mask ROM product
Flash memory product
(read protection)
Evaluation product
(for development)
ROM size
16 K
× 8 bits
(internal mask ROM)
16 K
× 8 bits
(internal flash)
32 K
× 8 bits
(external EPROM)
RAM size
512
× 8 bits
CPU functions
Number of instructions :
Instruction bit length :
Instruction length :
Data bit length :
Minimum execution time :
Interrupt processing time :
136
8 bits
1 to 3 bytes
1, 8, 16 bits
0.32
μs to 5.1 μs (12.5 MHz)
2.88
μs to 46.1 μs (12.5 MHz)
Ports
General-purpose I/O ports (CMOS) : 26 (also serve as peripherals )
(4 ports are also an N-ch open-drain type.)
21-bit
time-base timer
21-bit Interrupt cycle : 0.66 ms, 2.64 ms, 21 ms, or 335.5 ms with 12.5 MHz main clock
Watchdog timer
Reset generation cycle : 335.5 ms minimum with 12.5 MHz main clock
8-bit PWM timer
8-bit interval timer operation (square output capable, operating clock cycle :
0.32
μs , 2.56 μs, 5.1 μs, 20.5 μs)
8-bit resolution PWM operation (conversion cycle : 81.9
μs to 21.47 s : in the selection
of internal shift clock of 8/16-bit capture timer)
Count clock selectable between 8-bit and 16-bit timer/counter outputs
8/16-bit
capture, timer/counter
External captured input selectable
8-bit capture timer/counter
× 1 channel + 8-bit timer or
16-bit capture timer/counter
× 1 channel
Capable of event count operation and square wave output with 8-bit timer 0 or 16-bit
counter
UART
Transfer data length : 6/7/8 bits
8-bit Serial I/O
8 bits LSB first/MSB first selectable
One clock selectable from four operation clocks
(one external shift clock, three internal shift clocks : 0.8
μs, 6.4 μs, 25.6 μs)
12-bit PPG timer
Output frequency : Pulse width and cycle selectable
External interrupt 1
(wake-up function)
3 independent channels (Interrupt vector, request flag, request output enabled)
Rising/falling/both edge selectable
Used for wake-up from stop/sleep mode. (Edge detection is also permitted in the stop
mode.)
External interrupt 2
(wake-up function)
8 channels (low-level interrupt only)
Used for wake-up from stop/sleep mode. (Edge detection is also permitted in the stop
mode.)
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