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參數(shù)資料
| 型號(hào)： | MB89P857P-SH |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-bit Proprietary Microcontroller |
| 中文描述： | 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PDIP64 |
| 封裝： | SHRINK, PLASTIC, DIP-64 |
| 文件頁(yè)數(shù)： | 21/48頁(yè) |
| 文件大?。?/td> | 677K |
| 代理商： | MB89P857P-SH |
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MB89850R Series
21
(Continued)
Notes: Do not use vacancies.
When a read-modify-write instruction (such as bit set) is used to access a write-only register or a register
containing a write-only bit, a bit designated by the instruction will have a predetermined value. However,
a write-only bit included, if any, in bits not defined by the instruction will cause a malfunction. So no access
to the register should be tried with any read-modefy-write instruction.
Address
Read/write
Register name
Register description
26
H
(R/W)
EIC1
External interrupt control register 1
27
H
(R/W)
EIC2
External interrupt control register 2
28
H
(R/W)
ADC1
A/D converter control register 1
29
H
(R/W)
ADC2
A/D converter control register 2
2A
H
(R)
ADDH
A/D converter data register (H)
2B
H
(R)
ADDL
A/D converter data register (L)
2C
H
Vacancy
2D
H
(W)
ZOCTR
Zero detection output control register
2E
H
(W)
CLRBRH
Compare clear buffer register (H)
2F
H
(W)
CLRBRL
Compare clear buffer register (L)
30
H
(R/W)
TCSR
Timer control status register
31
H
(R/W)
CICR
Compare interrupt control register
32
H
(R/W)
TMCR
Timer mode control register
33
H
(R/W)
COER
Compare/port selection register
34
H
(R/W)
CMCR
Compare buffer mode control register
35
H
(R/W)
DTCR
Dead-time timer control register
36
H
(W)
DTSR
Dead-time setting register
37
H
(R/W)
OCTBR
Output control buffer register
38
H
(W)
OCPBR0H
Output compare buffer register 0 (H)
39
H
(W)
OCPBR0L
Output compare buffer register 0 (L)
3A
H
(W)
OCPBR1H
Output compare buffer register 1 (H)
3B
H
(W)
OCPBR1L
Output compare buffer register 1 (L)
3C
H
(W)
OCPBR2H
Output compare buffer register 2 (H)
3D
H
(W)
OCPBR2L
Output compare buffer register 2 (L)
3E
H
(W)
OCPBR3H
Output compare buffer register 3 (H)
3F
H
(W)
OCPBR3L
Output compare buffer register 3 (L)
40
H
to 7B
H
Vacancy
7C
H
(W)
ILR1
Interrupt level setting register 1
7D
H
(W)
ILR2
Interrupt level setting register 2
7E
H
(W)
ILR3
Interrupt level setting register 3
7F
H
Vacancy
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