參數(shù)資料
型號(hào): MB89P915P-101-SH
廠商: FUJITSU LTD
元件分類(lèi): 微控制器/微處理器
英文描述: VIDEO SPLIT CBL PVC MM 10
中文描述: 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDIP48
封裝: SHRINK, PLASTIC, DIP-48
文件頁(yè)數(shù): 39/53頁(yè)
文件大?。?/td> 673K
代理商: MB89P915P-101-SH
39
MB89910 Series
7. Notes on Using A/D Converter
Input impedance of the analog input pins
The A/D converter used for the MB89910 series contains a sample hold circuit as illustrated below to fetch
analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low. If a higher accurancy is required, set the output impedance in this series
to 2 k
or less
.
Note that if the impedance cannot be kept low output impedance, it is recommended either to use the software
to continuously activate the A/D converter for simulating longer sampling time or to connect an external
capacitor of approx. 0.1
μ
F to the analog input pin.
Error
The smaller the | AVR – AV
SS
|, the greater the error would become relatively.
1111 1111
1111 1110
0000 0010
0000 0001
0000 0000
V
OT
V
NT
V
(N + 1)T
V
FST
Digital output
(1 LSB
×
N + V
OT
)
Analog input
Actual conversion value
Theoretical conversion value
Linearity error
1 LSB
1 LSB =
AVR
256
Linearity error =
Differential linearity error =
Total error =
V
NT
– (1 LSB
×
N + V
OT
)
1 LSB
V
( N + 1 ) T
– V
NT
1 LSB
V
NT
– (1 LSB
×
N + 0.5 LSB)
– 1
Sample hold circuit
C .
Analog channel selector
Close for 8 instruction cycles after activating
A/D conversion.
If the output
impedance of external
circuit is high
,
it is
recommended to
connect an external
capacitor of approx.
0.1
μ
F.
Analog input pin
Comparator
R .
Analog Input Equivalent Circuit
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