參數(shù)資料
型號(hào): MB89P965PFM
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP48
封裝: 10 X 10 MM, 0.80 MM PITCH, PLASTIC, QFP-48
文件頁(yè)數(shù): 269/278頁(yè)
文件大小: 1847K
代理商: MB89P965PFM
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68
CHAPTER 3 CPU
MB89960 series
3.7 Standby Modes
3.7.4 Notes on Using Standby Modes
The device does not change to a standby mode if an interrupt request from a
peripheral function is present when the standby mode is set in the standby control
register (STBC). Also, if an interrupt is used to recover from a standby mode to the
normal operating state, the operation after recovery differs depending on whether or
not the interrupt request is accepted.
s Changing to a Standby Mode and Interrupts
If an interrupt request from a peripheral function to the CPU is present, writing “1” to the stop bit
(STP) or sleep bit (SLP) of the standby control register (STBC) is ignored and the CPU does not
change to the standby mode. (The CPU also does not change to the standby mode after
completing interrupt processing.)
Provided the priority set in the interrupt level setting register (ILR1 - ILR3) corresponding to the
interrupt request is higher than “11” (but not including “11”), this does not depend on whether or
not the CPU accepts the interrupt. Even if the CPU is currently performing interrupt processing,
the interrupt request flag bit is cleared and, if no other interrupt request is present, the device
can change to the standby mode.
s Notes on Setting Standby Mode
The device changes to stop mode if the sleep bit of the standby control register (STBC: SLP)
and the stop bit of the standby control register (STBC: STP) are set to “1” simultaneously.
s Using an Interrupt to Release a Standby Mode
If an external or peripheral function interrupt request with an interrupt priority higher than “11”
occurs during sleep or stop mode, the standby mode is released. This does not depend on
whether or not the CPU accepts the interrupt.
The device performs the normal operations after releasing the standby mode. If the priority set
in the interrupt level setting register (ILR1 - ILR3) corresponding to the interrupt request is
higher than the interrupt level bits in the condition code register (CCR: IL1, 0), and if the
interrupt enable flag is enabled (CCR: I = “1”), the CPU branches to the interrupt processing
routine. If the interrupt is not accepted, operation restarts from the instruction following the
instruction that entered the standby mode.
To prevent control from branching to an interrupt processing routine after recovery, take
measures such as disabling interrupts before initiating the standby mode.
s Oscillation Stabilization Delay Time
As the oscillator that provides the source oscillation is halted during stop mode, a delay time is
required for oscillation to stabilize after the oscillator restarts operation. The oscillation
stabilization delay time can be selected as an option by specifying the oscillation stabilization
delay time bit in the counter of the time-based timer. Add the Regulator Recovery Time also.
If the interval time set for the time-based timer is less than the oscillation stabilization delay
time, the time-based timer generates an interval timer interrupt request before the end of the
oscillation stabilization delay time. To prevent this, disable the interrupt request output for the
time-based timer (TBTC: TBIE = “0”) before changing to stop mode.
相關(guān)PDF資料
PDF描述
MB89965PF-G-XXX 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP48
MB89965PFM-G-XXX 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP48
MB89965PFV-G-XXX 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP64
MB89P965PFV 8-BIT, OTPROM, 10 MHz, MICROCONTROLLER, PQFP64
MB89F202RAPFV-GE1 8-BIT, FLASH, 12.5 MHz, MICROCONTROLLER, PDSO34
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