參數(shù)資料
型號: MB90561AP
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-bit Proprietary Microcontrollers
中文描述: 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP64
封裝: 1.788 MM PITCH, SHRINK, PLASTIC, DIP-64
文件頁數(shù): 49/91頁
文件大?。?/td> 484K
代理商: MB90561AP
MB90560/565 Series
49
8.
Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Generation of this
hardware interrupt can be specified by software.
Delayed interrupt generation module functions
Block diagram
Function and Control
Interrupt trigger
Writing “1” to bit R0 of the delayed interrupt request generation/clear register
(DIRR : R0
=
1) generates an interrupt request.
Writing “0” to bit R0 of the delayed interrupt request generation/clear register
(DIRR : R0
=
1) clears the interrupt request.
No enable/disable register is provided for this interrupt.
Interrupt control
Interrupt flag
Set in bit R0 of the delayed interrupt request generation/clear register
(DIRR : R0) .
EI
2
OS support
Not supported by the extended intelligent I/O service (EI
2
OS) .
R0
Internal data bus
Delayed interrupt request generation/
clear register (DIRR)
: Undefined
S
R
Interrupt
request signal
Interrupt request
latch
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參數(shù)描述
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