參數(shù)資料
型號: MB90583CA
廠商: Fujitsu Limited
英文描述: Octal Bus Transceivers With 3-State Outputs 20-CDIP -55 to 125
中文描述: 16位微控制器專有
文件頁數(shù): 41/124頁
文件大?。?/td> 2639K
代理商: MB90583CA
MB90580C Series
41
3.
Watchdog Timer
The watchdog timer consists of a 2-bit watchdog counter using carry signals from the 18-bit time-base timer as
the clock source, a control register, and a watchdog reset control section.
(1) Register configuration
(2) Block Diagram
Watchdog timer control register
bit
7
6
5
4
3
2
1
0
Address
: 0000A8
H
PONR STBR WRST ERST SRST WTE WT1
(R)
(R)
(R)
(R)
(X)
(X)
(X)
(X)
WT0
WDTC
Access
(R)
(X)
(W) (W) (W)
(1)
(1)
Initial value
(1)
TBTC
PONR
STBR
WRST
ERST
SRST
TBC0
TBR
TBIE
TBOF
TBC1
WT1
WT0
WTE
WTC
WDCS
SCE
WTC2
WTC1
WTC0
WTR
WTIE
WTOF
WDTC
WDTC
AND
CLR
OF
CLR
2
12
2
14
2
16
2
19
TBTRES
2
9
2
10
2
11
2
12
2
13
2
14
2
15
WTRES
2
11
2
13
2
15
2
18
2
10
2
13
2
14
2
15
Clock timer
Q
R
S
AND
Q
R
S
AND
Q
R
S
Time-base
interrupt
Clock
interrupt
Selector
Selector
Selector
Main clock
Clock input
Time-base timer
Watchdog reset
generator
2-bit
counter
Clock input
To WDGRST
internal reset
generator
From power-on reset
generator
From hardware
standby control circuit
Subclock
From RST bit in STBYC
register
From RST pin
F
2
M
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