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參數(shù)資料
| 型號： | MB90598 |
| 廠商： | Fujitsu Limited |
| 英文描述： | Quadruple 2-Input Positive-OR Gate 14-CDIP -55 to 125 |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 24/47頁 |
| 文件大?。?/td> | 657K |
| 代理商： | MB90598 |
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MB90595/595G Series
24
I
CAN CONTROLLER
The CAN controller has the following features:
Conforms to CAN Specification Version 2.0 Part A and B
- Supports transmission/reception in standard frame and extended frame formats
Supports transmission of data frames by receiving remote frames
16 transmitting/receiving message buffers
- 29-bit ID and 8-byte data
- Multi-level message buffer configuration
Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message
buffer as 1D acceptance mask
- Two acceptance mask registers in either standard frame format or extended frame formats
Bit rate programmable from 10 Kbit/s to 2 Mbit/s (when input clock is at 16 MHz)
List of Control Registers
(Continued)
Address
Register
Abbreviation
Access
Initial Value
000080
H
Message buffer valid register
BVALR
R/W
00000000 00000000
B
000081
H
000082
H
Transmit request register
TREQR
R/W
00000000 00000000
B
000083
H
000084
H
Transmit cancel register
TCANR
W
00000000 00000000
B
000085
H
000086
H
Transmit complete register
TCR
R/W
00000000 00000000
B
000087
H
000088
H
Receive complete register
RCR
R/W
00000000 00000000
B
000089
H
00008A
H
Remote request receiving register
RRTRR
R/W
00000000 00000000
B
00008B
H
00008C
H
Receive overrun register
ROVRR
R/W
00000000 00000000
B
00008D
H
00008E
H
Receive interrupt enable register
RIER
R/W
00000000 00000000
B
00008F
H
001B00
H
Control status register
CSR
R/W, R
00---000 0----0-1
B
001B01
H
001B02
H
Last event indicator register
LEIR
R/W
-------- 000-0000
B
001B03
H
001B04
H
Receive/transmit error counter
RTEC
R
00000000 00000000
B
001B05
H
001B06
H
Bit timing register
BTR
R/W
-1111111 11111111
B
001B07
H
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