參數(shù)資料
型號(hào): MB90F378PFF-GE1
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-bit Proprietary Microcontroller
中文描述: 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP144
封裝: 0.40 MM PITCH, PLASTIC, LQFP-144
文件頁(yè)數(shù): 6/65頁(yè)
文件大小: 323K
代理商: MB90F378PFF-GE1
MB90378 Series
6
PIN DESCRIPTION
(Continued)
Pin no.
Pin name
I/O
circuit
Pin status
during
reset
Function
LQFP-144
128,129
X0,X1
A
Oscillating
Main oscillation I/O pins.
20,21
X0A,X1A
A
Oscillating
Sub-clock oscillation I/O pins.
17
RST
B
Reset input External reset input pin.
58, 57, 56
MD0 to
MD2
C
Mode input
Input pin for operation mode specification. Connect this pin
directly to Vcc or Vss.
109 to 116
P00 to P07
D
Port input
General-purpose I/O ports.
KSI0 to
KSI7
Can be used as key-on wake-up interrupt input ch 0 to 7. Input
is enabled when 1 is set in EICR : EN0 to 7 in standby mode.
117 to 124 P10 to P17
E
General-purpose I/O ports.
125,
130 to 136
P20 to P27
E
General-purpose I/O ports.
137, 138
P30, P31
E
General-purpose I/O ports.
PG00,
PG01
8/16-bit PPG timer output pins.
8-bit x 2 channels mode use : Event output from PG00/PG01
16-bit x 1channel mode use : Event output from PG00
139, 140
P32, P33
E
General-purpose I/O ports.
PG10,
PG11
8/16-bit PPG timer output pins.
8-bit x 2 channels mode use : Event output from PG10/PG11.
16-bit x 1channel mode use : Event output from PG10.
141 to 143 P34 to P36
E
General-purpose I/O ports.
144
P37
E
General-purpose I/O port.
ADTG
External trigger input pin (ADTG) for the A/D converter.
1
P40
F
General-purpose Nch open-drain I/O port.
PSCK0
Serial clock I/O pin for PS/2 interface ch 0. This function is
selected when PS/2 interface ch 0 is enabled.
2
P41
F
General-purpose Nch open-drain I/O port.
PSDA0
Serial data I/O pin for PS/2 interface ch 0. This function is
selected when PS/2 interface ch 0 is enabled.
3
P42
F
General-purpose Nch open-drain I/O port.
PSCK1
Serial clock I/O pin for PS/2 interface ch 1. This function is
selected when PS/2 interface ch 1 is enabled.
4
P43
F
General-purpose Nch open-drain I/O port.
PSDA1
Serial data I/O pin for PS/2 interface ch 1. This function is
selected when PS/2 interface ch 1 is enabled.
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