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參數(shù)資料
| 型號： | MB90F444G |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 21/61頁 |
| 文件大?。?/td> | 644K |
| 代理商： | MB90F444G |
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MB90440G Series
21
(Continued)
Address
Register
Abbrevia-
tion
Read/
Write
Resource
name
Initial value
44
H
PPG6 operation mode control register
PPGC6
R/W
16-bit
Programable
Pulse
Generator 6/7
0_000__1
B
45
H
PPG7 operation mode control register
PPGC7
R/W
0_000001
B
46
H
PPG6 and PPG7 clock selection register
PPG67
R/W
000000__
B
47
H
to 4B
H
Reserved
4C
H
Input capture control status 0/1
ICS01
R/W
Input capture 0/1
00000000
B
4D
H
Input capture control status 2/3
ICS23
R/W
Input capture 2/3
00000000
B
4E
H
Input capture control status 4/5
ICS45
R/W
Input capture 4/5
00000000
B
4F
H
Input capture control status 6/7
ICS67
R/W
Input capture 6/7
00000000
B
50
H
Timer control status register 0
TMCSR0
R/W
16-bit
reload
timer 0
00000000
B
51
H
____0000
B
52
H
Timer register 0/reload register 0
TMR0/
TMRLR0
R/W
XXXXXXXX
B
53
H
XXXXXXXX
B
54
H
Timer control status register 1
TMCSR1
R/W
16-bit reload
timer 1
00000000
B
55
H
____0000
B
56
H
Timer register 1/Reload register 1
TMR1/
TMRLR1
R/W
XXXXXXXX
B
57
H
XXXXXXXX
B
58
H
Output compare control status register 0
OCS0
R/W
Output
compare 0/1
0000__00
B
59
H
Output compare control status register 1
OCS1
R/W
___00000
B
5A
H
Output compare control status register 2
OCS2
R/W
Output
compare 2/3
0000__00
B
5B
H
Output compare control status register 3
OCS3
R/W
___00000
B
5C
H
to 6B
H
Reserved for CAN 2 Interface
6C
H
Timer data register
TCDT
R/W
I/O timer
00000000
B
6D
H
00000000
B
6E
H
Timer control status register
TCCS
R/W
00000000
B
6F
H
ROM mirror function selection register
ROMM
R/W
ROM mirror
function selec-
tion module
_______1
B
70
H
to 7F
H
Reserved for CAN 0 Interface
80
H
to 8F
H
Reserved for CAN 1 Interface
90
H
to 9D
H
Prohibited area
9E
H
Program address detection control
status register
PACSR
R/W
Address match
detection
function
00000000
B
9F
H
Delayed interrupt/release register
DIRR
R/W
Delayed
interrupt genera-
tion module
_______0
B
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