MB90470 Series
26
(Continued)
Address
Register name
Symbol
Access
Resource name
Default
86
H
PWC2 division ratio register
DIVR2
R/W
PWC (ch2)
- - - - - - 0 0
87
H
Reserved
88
H
I
2
C bus status register
IBSR
R
I
2
C functions
0 0 0 0 0 0 0 0
89
H
I
2
C bus control register
IBCR
R/W
0 0 0 0 0 0 0 0
8A
H
I
2
C bus clock select register
ICCR
R/W
- - 0XXXXX
8B
H
I
2
C bus address register
IADR
R/W
- XXXXXXX
8C
H
I
2
C bus data register
IDAR
R/W
XXXXXXXX
8D
H
Reserved
8E
H
μ
PG control register
PGCSR
R/W
μ
PG
0 0 0 0 0 - - -
8F
H
to 9B
H
Prohibited
9C
H
μ
DMA status register
μ
DMA status register
Program address detection control
status resister
DSRL
R/W
μ
DMA
μ
DMA
0 0 0 0 0 0 0 0
9D
H
DSRH
R/W
0 0 0 0 0 0 0 0
9E
H
PACSR
R/W
Address Match
Detection Function
0 0 0 0 0 0 0 0
9F
H
Delay interrupt source generate/
release register
DIRR
R/W
Delay interrupt
generator module
- - - - - - - - 0
A0
H
Low power mode register
LPMCR
R/W
Low power modes
0 0 0 1 1 0 0 0
A1
H
Clock select register
CKSCR
R/W
Low power modes
1 1 1 1 1 1 0 0
A2
H
, A3
H
Reserved
A4
H
μ
DMA stop status register
Auto ready function select register
DSSR
R/W
μ
DMA
0 0 0 0 0 0 0 0
A5
H
ARSR
W
External pins
0 0 1 1 - - 0 0
A6
H
External address output control
register
HACR
W
External pins
0 0 0 0 0 0 0 0
A7
H
Bus control signal control register
EPCR
W
External pins
1 0 0 0 * 1 0 -
A8
H
Watchdog control register
WDTC
R/W
Watchdog timer
XXXXX 1 1 1
A9
H
Time base timer control register
TBTC
R/W
Time base timer
1 X X 0 0 1 0 0
AA
H
Watch timer control register
WTC
R/W
Watch timer
1 0 0 0 1 0 0 0
AB
H
Reserved
AC
H
μ
DMA control register
μ
DMA control register
DERL
R/W
μ
DMA
μ
DMA
0 0 0 0 0 0 0 0
AD
H
DERH
R/W
0 0 0 0 0 0 0 0
AE
H
Flash memory control status register
FMCR
R/W
Flash memory
interface
0 0 0 X 0 0 0 0
AF
H
Prohibited
B0
H
Interrupt control register 00
ICR00
R/W
XXXX 0 1 1 1
B1
H
Interrupt control register 01
ICR01
R/W
XXXX 0 1 1 1
B2
H
Interrupt control register 02
ICR02
R/W
XXXX 0 1 1 1
B3
H
Interrupt control register 03
ICR03
R/W
XXXX 0 1 1 1