MB90470 Series
31
s PERIPHERAL RESOURCES
1.
I/O Ports
The I/O ports output data from the CPU to the I/O pins, and also load signals input at the I/O pins into the CPU,
according to the port register (PDR) . The ports can also control the input/output direction of the I/O pins in bit
units according to the port direction register (DDR) .
The MB90470 series has 82 input/output pins and two open drain output pins. Ports 0 through A are input/output
ports, and port 76, and 77 are the open drain ports.
(1) Port Registers
* : Input/output port read/write operations are somewhat different than reading and writing to memory, and operate
as follows.
Input mode
Read : Reads the signal level of the corresponding pin.
Write : Writes to the output latch.
Output mode
Read : Reads the value of the data register latch.
Write : Value is output to the corresponding pin.
PDR0
Default value
Access
Address : 000000H
Undefined
R/W*
PDR1
Address : 000001H
Undefined
R/W*
PDR2
Address : 000002H
Undefined
R/W*
PDR3
Address : 000003H
Undefined
R/W*
PDR4
Address : 000004H
Undefined
R/W*
PDR5
Address : 000005H
Undefined
R/W*
PDR6
Address : 000006H
Undefined
R/W*
PDR7
Address : 000007H
11XXXXXX
R/W*
PDR8
Address : 000008H
Undefined
R/W*
PDR9
Address : 000009H
Undefined
R/W*
PDRA
Address : 00000AH
Undefined
R/W*
76
5
4
3
2
1
0
P06
P07
P05
P04
P03
P02
P01
P00
76
5
4
3
2
1
0
P16
P17
P15
P14
P13
P12
P11
P10
76
5
4
3
2
1
0
P26
P27
P25
P24
P23
P22
P21
P20
76
5
4
3
2
1
0
P36
P37
P35
P34
P33
P32
P31
P30
76
5
4
3
2
1
0
P46
P47
P45
P44
P43
P42
P41
P40
76
5
4
3
2
1
0
P56
P57
P55
P54
P53
P52
P51
P50
76
5
4
3
2
1
0
P66
P67
P65
P64
P63
P62
P61
P60
76
5
4
3
2
1
0
P76
P77
P75
P74
P73
P72
P71
P70
76
5
4
3
2
1
0
P86
P87
P85
P84
P83
P82
P81
P80
76
5
4
3
2
1
0
P96
P97
P95
P94
P93
P92
P91
P90
76
5
4
3
2
1
0
PA3
PA2
PA1
PA0