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MB90470 Series
56
9.
I
2
C Interface
The I
2
C interface is a serial I/O port supporting Inter IC bus operation, and operates as a master/slave device
on the I
2
C bus. The following features are provided.
Master/slave sending and receiving
Arbitration functions
Clock synchronization functions
Slave address/general call address detection functions
Transfer direction detection function
Start condition repeat generator and detection function
Bus error detection function
(1) Register List
IBSR (bus status register)
IBCR (bus control register)
ICCR (clock control register)
IADR (address register)
IDAR (data register)
Bit no.
Address : 000088
H
Read/write
Default value
Bit no.
Address : 000089
H
Read/write
Default value
Bit no.
Address : 00008A
H
Read/write
Default value
Bit no.
Address : 00008B
H
Read/write
Default value
Bit no.
Address : 00008C
H
Read/write
Default value
( R )
( 0 )
( R )
( 0 )
( R )
( 0 )
( R )
( 0 )
( R )
( 0 )
( R )
( 0 )
( R )
( 0 )
7
6
5
4
3
2
1
0
RSC
( R )
( 0 )
BB
AL
LRB
TRX
AAS
GCA
FBT
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0)
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
(R/W)
( 0 )
15
14
13
12
11
10
9
8
BEIE
(R/W)
( 0 )
BER
SCC
MSS
ACK
GCAA
INTE
INT
(
)
(
)
(R/W)
( 0 )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
7
6
5
4
3
2
1
0
(
)
(
)
EN
CS4
CS3
CS2
CS1
CS0
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
15
14
13
12
11
10
9
8
A6
(
)
(
)
A5
A4
A3
A2
A1
A0
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
(R/W)
( X )
7
6
5
4
3
2
1
0
D6
(R/W)
( X )
D7
D5
D4
D3
D2
D1
D0