參數(shù)資料
型號(hào)： MB90F480
廠商： Fujitsu Limited
英文描述： 16-bit Proprietary Microcontroller CMOS
中文描述： 16位微控制器專有的CMOS
文件頁(yè)數(shù)： 23/113頁(yè)
文件大?。?/td> 522K
代理商： MB90F480
MB90480/485 Series
23
(Continued)
Address
Register name
Abbreviated
register name
UDCR0
UDCR1
RCR0
RCR1
CCRL0
CCRH0
(Reserved area)
ROMM
CCRL1
CCRH1
CSR0
(Reserved area)
CSR1
(Reserved area)
Read/
Write
R
R
W
W
R/W
R/W
Resource name
Initial value
68
H
69
H
6A
H
6B
H
6C
H
6D
H
6E
H
6F
H
70
H
71
H
72
H
73
H
74
H
75
H
76
H
*
77
H
*
78
H
*
79
H
*
7A
H
*
7B
H
*
7C
H
*
7D
H
*
7E
H
*
7F
H
*
80
H
*
81
H
*
82
H
*
83
H
84
H
*
85
H
86
H
*
87
H
88
H
*
89
H
*
8A
H
*
8B
H
*
8C
H
*
8D
H
8E
H
*
Up/down count register ch0
Up/down count register ch1
Reload/compare register ch0
Reload/compare register ch1
Counter control register lower digits ch0
Counter control register upper digits ch0
8/16-bit up/down timer
counter
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 X 0 0 X 0 0 0
B
0 0 0 0 0 0 0 0
B
ROM mirror function select register
Counter control register lower digits ch1
Counter control register upper digits ch1
Counter status register ch0
R/W ROM mirroring function
R/W
8/16-bit up/down timer
counter
R/W
- - - - - - 0 1
B
0 X 0 0 X 0 0 0
B
- 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
R/W
Counter status register ch1
R/W
8/16-bit UDC
0 0 0 0 0 0 0 0
B
PWC control status register
PWCSR0
R/W
PWC timer (ch0)
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 X
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 X
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 X
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
- - - - - - 0 0
B
PWC data buffer register
PWCR0
R/W
PWC control status register
PWCSR1
R/W
PWC timer (ch 1)
PWC data buffer register
PWCR1
R/W
PWC control status register
PWCSR2
R/W
PWC timer (ch2)
PWC data buffer register
PWCR2
R/W
Dividing ratio control register
DIVR0
(Reserved area)
DIVR1
(Reserved area)
DIVR2
(Reserved area)
IBSR
IBCR
ICCR
IADR
IDAR
(Reserved area)
PGCSR
(Disabled)
DSRL
R/W
PWC (ch0)
Dividing ratio control register
R/W
PWC (ch1)
- - - - - - 0 0
B
Dividing ratio control register
R/W
PWC (ch2)
- - - - - - 0 0
B
Bus status register
Bus control register
Bus clock control register
Bus address register
Bus data register
R
I
2
C
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
- - 0 X X X X X
B
- X X X X X X X
B
XXXXXXXX
B
R/W
R/W
R/W
R/W
μ
PG control status register
R/W
μ
PG
0 0 0 0 0 - - -
B
8F
H
to 9B
H
9C
H
μ
DMA status register
R/W
μ
DMA
0 0 0 0 0 0 0 0
B
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