![](http://datasheet.mmic.net.cn/330000/MB90487PFV_datasheet_16437531/MB90487PFV_22.png)
MB90480/485 Series
22
(Continued)
Address
Register name
Abbreviated
register
name
PPG45
(Reserved area)
ADCS1
ADCS2
ADCR1
ADCR2
Read/
Write
Resource name
Initial value
44
H
45
H
46
H
47
H
48
H
49
H
4A
H
4B
H
4C
H
4D
H
4E
H
4F
H
50
H
51
H
52
H
53
H
54
H
55
H
56
H
57
H
58
H
59
H
5A
H
5B
H
5C
H
5D
H
5E
H
5F
H
60
H
61
H
62
H
63
H
64
H
65
H
66
H
67
H
PPG4, 5 output control register
R/W
8/16-bit PPG
0 0 0 0 0 0 0 0
B
Control status register
R/W
R/W
R
R
A/Dconverter
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
XXXXXXXX
B
0 0 0 0 0 XXX
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 - - 0 0
B
- - - 0 0 0 0 0
B
0 0 0 0 - - 0 0
B
- - - 0 0 0 0 0
B
0 0 0 0 - - 0 0
B
- - - 0 0 0 0 0
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
XXXXXXXX
B
0 0 0 0 0 0 0 0
B
Data register
Output compare register (ch0) lower digits
Output compare register (ch0) upper digits
Output compare register (ch1) lower digits
Output compare register (ch1) upper digits
Output compare register (ch2) lower digits
Output compare register (ch2) upper digits
Output compare register (ch3) lower digits
Output compare register (ch3) upper digits
Output compare register (ch4) lower digits
Output compare register (ch4) upper digits
Output compare register (ch5) lower digits
Output compare register (ch5) upper digits
Output compare control register (ch0)
Output compare control register (ch1)
Output compare control register (ch2)
Output compare control register (ch3)
Output compare control register (ch4)
Output compare control register (ch5)
Input capture data register (ch0) lower digits
Input capture data register (ch0) upper digits
Input capture data register (ch1) lower digits
Input capture data register (ch1) upper digits
Input capture control register
OCCP0
R/W
16-bit output timer
output compare
(ch0 to ch5)
OCCP1
R/W
OCCP2
R/W
OCCP3
R/W
OCCP4
R/W
OCCP5
R/W
OCS0
OCS1
OCS2
OCS3
OCS4
OCS5
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R/W
IPCP0
16-bit output timer
input capture
(ch0, ch1)
IPCP1
ICS01
(Reserved area)
TCDT
TCDT
TCCS
TCCS
Timer counter data register lower digits
Timer counter data register upper digits
Timer control status register
Timer control status register
Compare clear register lower digits
Compare clear register upper digits
R/W
R/W
R/W
R/W
16-bit output timer
free run timer
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 0 0 0 0 0 0 0
B
0 - - 0 0 0 0 0
B
XXXXXXXX
B
XXXXXXXX
B
CPCLR
R/W