參數(shù)資料
型號(hào): MB90F488BPMC
廠商: FUJITSU LTD
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 25 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, PLASTIC, LQFP-100
文件頁數(shù): 45/124頁
文件大?。?/td> 3283K
代理商: MB90F488BPMC
MB90480B/485B Series
DS07-13722-11E
27
(Continued)
Address
Register name
Abbreviated
register
name
Read/
Write
Resource name
Initial value
62H
Timer counter data register lower digits
TCDT
R/W
16-bit input/output
timer free-run timer
00000000B
63H
Timer counter data register upper digits
TCDT
R/W
00000000B
64H
Timer counter control status register
TCCS
R/W
00000000B
65H
Timer counter control status register
TCCS
R/W
0--00000B
66H
Compare clear register lower digits
CPCLR
R/W
XXXXXXXXB
67H
Compare clear register upper digits
XXXXXXXXB
68H
Up/down count register (ch.0)
UDCR0
R
8/16-bit up/down
counter/timer
00000000B
69H
Up/down count register (ch.1)
UDCR1
R
00000000B
6AH
Reload/compare register (ch.0)
RCR0
W
00000000B
6BH
Reload/compare register (ch.1)
RCR1
W
00000000B
6CH
Counter control register (ch.0)
lower digits
CCRL0
W, R/W
0X00X000B
6DH
Counter control register (ch.0)
upper digits
CCRH0
R/W
00000000B
6EH
(Reserved area)
6FH
ROM mirror function select register
ROMM
R/W
ROM mirroring
function
------+1B
70H
Counter control register (ch.1)
lower digits
CCRL1
W, R/W
8/16-bit up/down
counter/timer
0X00X000B
71H
Counter control register (ch.1)
upper digits
CCRH1
R/W
-0000000B
72H
Counter status register (ch.0)
CSR0
R, R/W
00000000B
73H
(Reserved area)
74H
Counter status register (ch.1)
CSR1
R, R/W
8/16-bit UDC
00000000B
75H
(Reserved area)
76H*
PWC control/status register
PWCSR0
R, R/W
PWC (ch.0)
00000000B
77H*
0000000XB
78H*
PWC data buffer register
PWCR0
R/W
00000000B
79H*
00000000B
7AH*
PWC control/status register
PWCSR1
R, R/W
PWC (ch.1)
00000000B
7BH*
0000000XB
7CH*
PWC data buffer register
PWCR1
R/W
00000000B
7DH*
00000000B
7EH*
PWC control/status register
PWCSR2
R, R/W
PWC (ch.2)
00000000B
7FH*
0000000XB
80H*
PWC data buffer register
PWCR2
R/W
00000000B
81H*
00000000B
82H*
Dividing ratio control register
DIVR0
R/W
PWC (ch.0)
------00B
83H
(Reserved area)
84H*
Dividing ratio control register
DIVR1
R/W
PWC (ch.1)
------00B
85H
(Reserved area)
86H*
Dividing ratio control register
DIVR2
R/W
PWC (ch.2)
------00B
87H
(Reserved area)
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