參數(shù)資料
型號(hào)： MB90F584CPMC
元件分類(lèi)： 微控制器/微處理器
英文描述： MICROCONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.70 MM HEIGHT, 0.65 MM PITCH, PLASTIC, LQFP-100
文件頁(yè)數(shù)： 83/112頁(yè)
文件大小： 2372K
代理商： MB90F584CPMC
MB90580C Series
72
DS07-13710-6E
18. Address Match Detection Function
When an address matches the value set in the address detection register, the instruction code to be loaded into
the CPU is forced to be replaced with the INT9 instruction code (01H). When executing a set instruction, the
CPU executes the INT9 instruction. The address match detection function is implemented by processing using
the INT9 interrupt routine.
The device contains two address detection registers, each provided with a compare enable bit. When the value
set in the address detection register matches an address and the interrupt enable bit is “1”, the instruction code
to be loaded into the CPU is forced to be replaced with the INT9 instruction code.
(1) Register configuration
Program address detection register 0 to 2 (PADR0)
bit
PADR0 (lower)
Address
: 001FF0H
Access
Initial value
bit
PADR0 (middle)
Address
: 001FF1H
Access
Initial value
bit
PADR0 (upper)
Address
: 001FF2H
Access
Initial value
Program address detection register 3 to 5 (PADR1)
bit
PADR1 (lower)
Address
: 001FF3H
Access
Initial value
bit
PADR1 (middle)
Address
: 001FF4H
Access
Initial value
bit
PADR1 (upper)
Address
: 001FF5H
Access
Initial value
Program address detection control/status register (PACSR)
bit
76543210
Address
: 00009EH
Re-
served
Re-
served
Re-
served
Re-
served
AD1E
Re-
served
AD0E
Re-
served
Access
(
)
(
)
(
)
(
) (R/W)
(
) (R/W)
(
)
Initial value
(0)
76
54
3
2
10
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
17
16
15
14
13
12
11
10
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
76
54
3
2
10
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
17
16
15
14
13
12
11
10
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
76
54
3
2
10
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
17
16
15
14
13
12
11
10
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
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