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參數(shù)資料
| 型號： | MB90F823PFM |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Scan Test Devices With Octal Bus Transceivers 24-CDIP -55 to 125 |
| 中文描述： | 16位微控制器專有 |
| 文件頁數(shù)： | 49/98頁 |
| 文件大?。?/td> | 1415K |
| 代理商： | MB90F823PFM |
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MB90820 Series
49
7.
Multi-functional Timer
The 16-bit multi-functional timer module consists of one 16-bit free-running timer, four input capture circuits, six
output comparators and one channel of 16-bit PPG timer. This module allows six independent waveforms
generated by PPG timer or waveform generator to be outputted. With the 16-bit free-running timer and the input
capture circuit, input pulse width and external clock period measurement can be done.
(1) 16-bit free-running timer (1 channel)
The 16-bit free-running timer consists of a 16-bit up/up-down counter, timer control status register, 16-bit
compare clear register (with buffer register) and a prescaler.
8 types of counter operation clock (
φ
,
φ
/2,
φ
/4,
φ
/8,
φ
/16,
φ
/32,
φ
/64,
φ
/128) can be selected.
(φ
is the machine
clock.)
Two types of interrupt causes :
- Compare clear interrupt is generated when there is a comparing match with compare clear register and 16-
bit free-running timer.
- Zero detection interrupt is generated while 16-bit free-running timer is detected as zero in count value.
EI
2
OS supported.
Compare-clear register buffer provided :
The selectable buffer enables the 16-bit free-running timer update its compare-clear register automatically
without stop the timer operation. User can read the next compare-clear value to the compare-clear register
when the timer is running. The compare-clear register will be updated when the timer value is “0000
H
”
Reset, software clear, compare match with compare clear register in up-count mode will reset the counter
value to “0000
H
”.
Supply clock to output compare module :
The prescaler output is acted as the count clock of the output compare.
(2) Output compare module ( 6 channels)
The output compare module consists of six 16-bit output compare registers (with selectable buffer register),
compare output latch and compare control registers. An interrupt is generated and output level is inverted
when the value of 16-bit free-running timer and output compare register are matched.
6 output compare registers can be operated independently.
Output pins and interrupt flag are corresponding to each output compare register.
2 output compare registers can be paired to control the output pins.
Inverts output pins by using 2 output compare registers together.
Setting the initial value for each output pin is possible.
Interrupt is generated when there is a comparing match with output compare register and 16-bit free-running
timer.
EI
2
OS supported.
(3) Input capture module (4 channels)
Input capture consists of 4 independent external input pins, the corresponding input capture data register and
input capture control status register. By detecting any edge of the input signal from the external pin, the value
of the 16-bit free-running timer can be stored in the capture register and an interrupt is generated simultaneously.
Operations synchronized with the 16-bit free-running timer’s count clock.
3 types of trigger edge (rising edge, falling edge and both edge) of the external input signal can be selected
and there is indication bit to show the trigger edge is rising or falling.
4 input captures can be operated independently.
Two independent interrupts are generated when detecting a valid edge from external input.
EI
2
OS supported.
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