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參數(shù)資料
| 型號： | MB90F867EPF |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100 |
| 文件頁數(shù)： | 51/68頁 |
| 文件大?。?/td> | 1040K |
| 代理商： | MB90F867EPF |
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MB90860E Series
55
(13) I2C Timing
(TA
= –40°C to +105°C, VCC = 5.0 V ± 10%, VSS = 0.0 V)
*1 : For use at over 100 kHz, set the machine clock to at least 6 MHz.
*2 : R,C : Pull-up resistance and load capacitance of the SCL and SDA lines.
*3 : The maximum tHDDAT must be satisfied if the device does not extend the “L” width (tLOW) of the SCL signal.
*4 : A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement
tSUDAT
≥ 250 ns must then be met.
Parameter
Symbol
Condition
Standard-mode
Fast-mode*1
Unit
Min
Max
Min
Max
SCL clock frequency
fSCL
R
= 1.7 k,
C
= 50 pF*2
0
100
0
400
kHz
Hold time (repeated) START condition
SDA
↓ → SCL ↓
tHDSTA
4.0
0.6
s
“L” width of the SCL clock
tLOW
4.7
1.3
s
“H” width of the SCL clock
tHIGH
4.0
0.6
s
Set-up time for a repeated START condition
SCL
↑ → SDA ↓
tSUSTA
4.7
0.6
s
Data hold time
SCL
↓ → SDA ↓ ↑
tHDDAT
0
3.45*3
00.9*4
s
Data set-up time
SDA
↓ ↑ → SCL ↑
tSUDAT
250
100
ns
Set-up time for STOP condition
SCL
↑ → SDA ↑
tSUSTO
4.0
0.6
s
Bus free time between a STOP and START
condition
tBUS
4.7
1.3
s
SDA
SCL
tLOW
tSUDAT
tHDSTA
tBUS
tHDSTA
tHDDAT
tHIGH
tSUSTA
tSUSTO
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