參數(shù)資料
型號(hào): MB90F867ESPF
元件分類(lèi): 微控制器/微處理器
英文描述: 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100
封裝: 14 X 20 MM, 3.35 MM HEIGHT, 0.65 MM PITCH, PLASTIC, QFP-100
文件頁(yè)數(shù): 48/68頁(yè)
文件大?。?/td> 1040K
代理商: MB90F867ESPF
MB90860E Series
52
(9) UART0/1/2/3/4
(TA
= 40 °C to +105 °C, VCC = 5.0 V ± 10%, fCP ≤ 24 MHz, VSS = 0.0 V)
Notes :
AC characteristic in CLK synchronized mode.
CL is the load capacitance applied to the pins during testing.
Parameter
Symbol
Pin
Condition
Value
Unit
Min
Max
Serial clock cycle time
tSCYC
SCK0 to SCK4
Internal shift clock
mode output pins are
CL
= 80 pF + 1 TTL.
8 tCP
ns
SCK
↓ → SOT delay time
tSLOV
SCK0 to SCK4,
SOT0 to SOT4
80
+80
ns
Valid SIN
→ SCK ↑
tIVSH
SCK0 to SCK4,
SIN0 to SIN4
100
ns
SCK
↑ → Valid SIN hold time
tSHIX
SCK0 to SCK4,
SIN0 to SIN4
60
ns
Serial clock “H” pulse width
tSHSL
SCK0 to SCK4
External shift clock
mode output pins are
CL
= 80 pF + 1 TTL.
4 tCP
ns
Serial clock “L” pulse width
tSLSH
SCK0 to SCK4
4 tCP
ns
SCK
↓ → SOT delay time
tSLOV
SCK0 to SCK4,
SOT0 to SOT4
150
ns
Valid SIN
→ SCK ↑
tIVSH
SCK0 to SCK4,
SIN0 to SIN4
60
ns
SCK
↑ → Valid SIN hold time
tSHIX
SCK0 to SCK4,
SIN0 to SIN4
60
ns
Internal Shift Clock Mode
SCK
2.4 V
tSCYC
0.8 V
SOT
0.8 V
2.4 V
0.8 V
tSLOV
SIN
VIL
VIH
tIVSH
VIL
VIH
tSHIX
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