![](http://datasheet.mmic.net.cn/330000/MB90F884SPMC_datasheet_16438058/MB90F884SPMC_20.png)
MB90880 Series
20
■
HANDLING DEVICES
1.
Maximum rated voltages for the prevention of latch-up
Be cautious not to exceed the absolute maximum rating.
CMOS ICs may cause latch-up, when a voltage higher than V
CC
or lower than V
SS
is applied to input or output
pins other than medium-to-high resistant pins, or when a voltage exceeding the rating is applied between VCC
and VSS pins.
If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of the
device. Take the utmost care not to let it occur.
Likewise, care must be taken not to allow the analog power supply (AV
CC
, AVRH) and analog input to exceed
the digital power supply (V
CC
) when turning on or off any analog system.
Handling unused pins
2.
Leaving unused input pins open may cause a malfunction or latch-up which leads to fatal damage to the device.
Therefore, they must be pulled up or down through at least 2 k
resistance. Also, any unused I/O pin should be
left open in the output state, or set to the input state and handled in the same way as an unused input pin.
Notes on using external clock
3.
Even when an external clock is being used, oscillation stabilization wait time is required for a power-on reset or
release from sub clock mode or stop mode. Note that 25 MHz is the upper limit on the external clock that can
be used. The following diagram shows an example of using an external clock.
4.
Handling power supply pins (V
CC
/V
SS
)
When multiple VCC and VSS pins supply pins are used, all the power supply pins must be connected to external
power and ground lines due to the device design, to reduce latch-up and unwanted radiation, prevent abnormal
operation of strobe signals caused by the rise in the ground level and to conform to the total output current rating.
Make sure to connect the VCC and VSS pins of this device via lowest impedance to power lines. It is recommended
that a bypass capacitor of around 0.1
μ
F be placed between the VCC and VSS pins near the device.
Crystal oscillator circuit
5.
Noises around X0/X1 or X0A/X1A pins may cause abnormal operations. It is strongly recommended to provide
bypass capacitors via shortest distance from X0/X1, X0A/X1A pins, crystal oscillator (or ceramic oscillator) and
ground lines and also not to allow the lines of the oscillation circuit to cross the lines of other circuits. This will
ensure stable operations of the printed circuit boards. Please ask each crystal maker to evaluate the oscillational
characteristics of the crystal and this device.
6.
Notes on PLL clock mode operation
If an oscillator comes off or clock input stops during PLL clock mode operation, this microcontroller may continue
its operation using a free-running frequency from a self-excited oscillation circuit within PLL. This is not a
guaranteed operation.
X0
X1
Open