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參數(shù)資料
| 型號(hào)： | MB90F884A |
| 廠商： | Fujitsu Limited |
| 英文描述： | 16-Bit Proprietary Microcontroller |
| 中文描述： | 16位微控制器專有 |
| 文件頁(yè)數(shù)： | 62/75頁(yè) |
| 文件大?。?/td> | 1083K |
| 代理商： | MB90F884A |
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MB90880 Series
62
b. Slave mode operation
(
V
CC
=
2.7 V
to
3.6 V
,
V
SS
=
0.0 V
,
T
A
=
40
°
C to
+
85
°
C)
High-speed mode
*1 : t
CP
is the cycle time for the internal operation clock. Refer to (1) “Clock timing ratings”.
*2 : The high-speed mode I
2
C bus device can be used in a standard mode I
2
C bus system. However, the device
must satisfy the required condition “t
SUDAT
≥
250 ns”. If the device does not extend the “L” period of the SCL
signal, the succeeding data must be output to the SDA line before a period of 1250 ns (the maximum time of
SDA/SCL rise
+
t
SUDAT
) in which the SCL line is open.
*3 : Set the internal operation clock to 6MHz or higher when using this over 100kHz.
*4 : “R” and “C” are the pull-up resistance and load capacitance of the SCL/SDA lines.
Parameter
Symbol
Condi-
tions
Standard mode
*
3
Unit
Min
Max
Min
Max
SCL clock frequency
f
SCL
R=1k
C=50pF*
4
0
100
0
400
kHz
μ
s
μ
s
SCL clock “L” width
t
LOW
4.7
1.3
SCL clock “H” width
t
HIGH
4.0
0.6
Bus-free time between “stop”
condition and “start” condition
t
BUS
4.7
1.3
μ
s
Repeat “start” condition setup time
SCL
↑
→
SDA
↓
(Repeat) “start” condition hold time
SDA
↓
→
SCL
↓
“Stop” condition setup time
SCL
↑
→
SDA
↑
Data hold time
SCL
↓
→
SDA
↓↑
Data setup time
SDA
↓↑
→
SCL
↑
t
SUSTA
4.7
0.6
μ
s
t
HDSTA
4.0
0.6
μ
s
t
SUSTO
4.0
0.6
μ
s
t
HDDAT
2tcp*
1
2tcp*
1
μ
s
t
SUDAT
250
100*
2
ns
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